Commit 94566c5b authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Suzuki K Poulose
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coresight: etm: Make cycle count threshold user configurable 



When cycle counting is enabled, we use a default threshold value i.e 0x100
for the instruction trace cycle counting.

This patch makes the cycle threshold user configurable via perf event
attributes( 'cc_threshold' => event->attr.config3[11:0] ), falling back
to the current default if unspecified.

Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: James Clark <james.clark@arm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230921033631.1298723-3-anshuman.khandual@arm.com
parent 4aff040b

drivers/hwtracing/coresight/coresight-etm-perf.c

+2 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); 
PMU_FORMAT_ATTR(sinkid,		"config2:0-31");

/* config ID - set if a system configuration is selected */

PMU_FORMAT_ATTR(configid,	"config2:32-63");

PMU_FORMAT_ATTR(cc_threshold,	"config3:0-11");





/*
@@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = { 
	&format_attr_preset.attr,

	&format_attr_configid.attr,

	&format_attr_branch_broadcast.attr,

	&format_attr_cc_threshold.attr,

	NULL,

};

drivers/hwtracing/coresight/coresight-etm4x-core.c

+7 −2
Original line number Diff line number Diff line
@@ -644,7 +644,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, 
	struct etmv4_config *config = &drvdata->config;

	struct perf_event_attr *attr = &event->attr;

	unsigned long cfg_hash;

	int preset;

	int preset, cc_threshold;



	/* Clear configuration from previous run */

	memset(config, 0, sizeof(struct etmv4_config));
@@ -667,7 +667,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev, 
	if (attr->config & BIT(ETM_OPT_CYCACC)) {

		config->cfg |= TRCCONFIGR_CCI;

		/* TRM: Must program this for cycacc to work */

		config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;

		cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;

		if (!cc_threshold)

			cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;

		if (cc_threshold < drvdata->ccitmin)

			cc_threshold = drvdata->ccitmin;

		config->ccctlr = cc_threshold;

	}

	if (attr->config & BIT(ETM_OPT_TS)) {

		/*