Commit 9495e668 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux 

Tariq Toukan says:

====================
mlx5-next 2024-12-16

The following pull-request contains mlx5 IFC updates.

* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Add device cap abs_native_port_num
  net/mlx5: qos: Add ifc support for cross-esw scheduling
  net/mlx5: Add support for new scheduling elements
  net/mlx5: Add ConnectX-8 device to ifc
  net/mlx5: ifc: Reorganize mlx5_ifc_flow_table_context_bits
====================

Link: https://patch.msgid.link/20241216124028.973763-1-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents bc6a5efe aeb3ec99

drivers/net/ethernet/mellanox/mlx5/core/rl.c

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar 
		return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN;

	case TSAR_ELEMENT_TSAR_TYPE_ETS:

		return cap & TSAR_TYPE_CAP_MASK_ETS;

	case TSAR_ELEMENT_TSAR_TYPE_TC_ARB:

		return cap & TSAR_TYPE_CAP_MASK_TC_ARB;

	}



	return false;
@@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie 
		return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP:

		return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT:

		return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT;

	}



	return false;

include/linux/mlx5/mlx5_ifc.h

+39 −20
Original line number Diff line number Diff line
@@ -1095,7 +1095,9 @@ struct mlx5_ifc_qos_cap_bits { 
	u8         log_esw_max_sched_depth[0x4];

	u8         reserved_at_10[0x10];



	u8         reserved_at_20[0xb];

	u8         reserved_at_20[0x9];

	u8         esw_cross_esw_sched[0x1];

	u8         reserved_at_2a[0x1];

	u8         log_max_qos_nic_queue_group[0x5];

	u8         reserved_at_30[0x10];
@@ -1103,7 +1105,8 @@ struct mlx5_ifc_qos_cap_bits { 


	u8         packet_pacing_min_rate[0x20];



	u8         reserved_at_80[0x10];

	u8         reserved_at_80[0xb];

	u8         log_esw_max_rate_limit[0x5];

	u8         packet_pacing_rate_table_size[0x10];



	u8         esw_element_type[0x10];
@@ -1590,12 +1593,14 @@ enum { 
	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,

	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,

	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,

	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,

};



struct mlx5_ifc_cmd_hca_cap_bits {

	u8         reserved_at_0[0x6];

	u8         page_request_disable[0x1];

	u8         reserved_at_7[0x9];

	u8         abs_native_port_num[0x1];

	u8         reserved_at_8[0x8];

	u8         shared_object_to_user_object_allowed[0x1];

	u8         reserved_at_13[0xe];

	u8         vhca_resource_manager[0x1];
@@ -4103,6 +4108,7 @@ enum { 
	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,

};



enum {
@@ -4111,34 +4117,41 @@ enum { 
	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,

	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,

	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,

	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,

};



enum {

	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,

	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,

	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,

	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,

};



enum {

	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,

	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,

	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,

	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,

};



struct mlx5_ifc_tsar_element_bits {

	u8         reserved_at_0[0x8];

	u8         traffic_class[0x4];

	u8         reserved_at_4[0x4];

	u8         tsar_type[0x8];

	u8         reserved_at_10[0x10];

};



struct mlx5_ifc_vport_element_bits {

	u8         reserved_at_0[0x10];

	u8         reserved_at_0[0x4];

	u8         eswitch_owner_vhca_id_valid[0x1];

	u8         eswitch_owner_vhca_id[0xb];

	u8         vport_number[0x10];

};



struct mlx5_ifc_vport_tc_element_bits {

	u8         traffic_class[0x4];

	u8         reserved_at_4[0xc];

	u8         eswitch_owner_vhca_id_valid[0x1];

	u8         eswitch_owner_vhca_id[0xb];

	u8         vport_number[0x10];

};
@@ -4163,7 +4176,9 @@ struct mlx5_ifc_scheduling_context_bits { 


	u8         max_average_bw[0x20];



	u8         reserved_at_e0[0x120];

	u8         max_bw_obj_id[0x20];



	u8         reserved_at_100[0x100];

};



struct mlx5_ifc_rqtc_bits {
@@ -6324,6 +6339,20 @@ struct mlx5_ifc_modify_other_hca_cap_in_bits { 
	struct     mlx5_ifc_other_hca_cap_bits other_capability;

};



struct mlx5_ifc_sw_owner_icm_root_params_bits {

	u8         sw_owner_icm_root_1[0x40];



	u8         sw_owner_icm_root_0[0x40];

};



struct mlx5_ifc_rtc_params_bits {

	u8         rtc_id_0[0x20];



	u8         rtc_id_1[0x20];



	u8         reserved_at_40[0x40];

};



struct mlx5_ifc_flow_table_context_bits {

	u8         reformat_en[0x1];

	u8         decap_en[0x1];
@@ -6342,20 +6371,10 @@ struct mlx5_ifc_flow_table_context_bits { 
	u8         lag_master_next_table_id[0x18];



	u8         reserved_at_60[0x60];

	union {

		struct {

			u8         sw_owner_icm_root_1[0x40];



			u8         sw_owner_icm_root_0[0x40];

		} sws;

		struct {

			u8         rtc_id_0[0x20];



			u8         rtc_id_1[0x20];



			u8         reserved_at_100[0x40];



		} hws;

	union {

		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;

		struct mlx5_ifc_rtc_params_bits hws;

	};

};