Commit 949c9ef5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq_urgent_for_v6.12_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq fixes from Borislav Petkov:

 - Fix a case for sifive-plic where an interrupt gets disabled *and*
   masked and remains masked when it gets reenabled later

 - Plug a small race in GIC-v4 where userspace can force an affinity
   change of a virtual CPU (vPE) in its unmapping path

 - Do not mix the two sets of ocelot irqchip's registers in the mask
   calculation of the main interrupt sticky register

- Other smaller fixlets and cleanups

* tag 'irq_urgent_for_v6.12_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/renesas-rzg2l: Fix missing put_device
  irqchip/riscv-intc: Fix SMP=n boot with ACPI
  irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()
  irqchip/gic-v4: Don't allow a VMOVP on a dying VPE
  irqchip/sifive-plic: Return error code on failure
  irqchip/riscv-imsic: Fix output text of base address
  irqchip/ocelot: Comment sticky register clearing code
  irqchip/ocelot: Fix trigger register address
  irqchip: Remove obsolete config ARM_GIC_V3_ITS_PCI
parents 2b4d2501 d038109a

drivers/irqchip/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -45,13 +45,6 @@ config ARM_GIC_V3_ITS 
	select IRQ_MSI_LIB

	default ARM_GIC_V3



config ARM_GIC_V3_ITS_PCI

	bool

	depends on ARM_GIC_V3_ITS

	depends on PCI

	depends on PCI_MSI

	default ARM_GIC_V3_ITS



config ARM_GIC_V3_ITS_FSL_MC

	bool

	depends on ARM_GIC_V3_ITS

drivers/irqchip/irq-gic-v3-its.c

+12 −6
Original line number Diff line number Diff line
@@ -797,8 +797,8 @@ static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, 
	its_encode_valid(cmd, desc->its_vmapp_cmd.valid);



	if (!desc->its_vmapp_cmd.valid) {

		if (is_v4_1(its)) {

		alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);

		if (is_v4_1(its)) {

			its_encode_alloc(cmd, alloc);

			/*

			 * Unmapping a VPE is self-synchronizing on GICv4.1,
@@ -817,13 +817,13 @@ static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, 
	its_encode_vpt_addr(cmd, vpt_addr);

	its_encode_vpt_size(cmd, LPI_NRBITS - 1);



	alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);



	if (!is_v4_1(its))

		goto out;



	vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));



	alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);



	its_encode_alloc(cmd, alloc);



	/*
@@ -3806,6 +3806,13 @@ static int its_vpe_set_affinity(struct irq_data *d, 
	struct cpumask *table_mask;

	unsigned long flags;



	/*

	 * Check if we're racing against a VPE being destroyed, for

	 * which we don't want to allow a VMOVP.

	 */

	if (!atomic_read(&vpe->vmapp_count))

		return -EINVAL;



	/*

	 * Changing affinity is mega expensive, so let's be as lazy as

	 * we can and only do it if we really have to. Also, if mapped
@@ -4463,9 +4470,8 @@ static int its_vpe_init(struct its_vpe *vpe) 
	raw_spin_lock_init(&vpe->vpe_lock);

	vpe->vpe_id = vpe_id;

	vpe->vpt_page = vpt_page;

	if (gic_rdists->has_rvpeid)

	atomic_set(&vpe->vmapp_count, 0);

	else

	if (!gic_rdists->has_rvpeid)

		vpe->vpe_proxy_event = -1;



	return 0;

drivers/irqchip/irq-mscc-ocelot.c

+8 −2
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static struct chip_props ocelot_props = { 
	.reg_off_ena_clr	= 0x1c,

	.reg_off_ena_set	= 0x20,

	.reg_off_ident		= 0x38,

	.reg_off_trigger	= 0x5c,

	.reg_off_trigger	= 0x4,

	.n_irq			= 24,

};
@@ -70,7 +70,7 @@ static struct chip_props jaguar2_props = { 
	.reg_off_ena_clr	= 0x1c,

	.reg_off_ena_set	= 0x20,

	.reg_off_ident		= 0x38,

	.reg_off_trigger	= 0x5c,

	.reg_off_trigger	= 0x4,

	.n_irq			= 29,

};
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data) 
	u32 val;



	irq_gc_lock(gc);

	/*

	 * Clear sticky bits for edge mode interrupts.

	 * Serval has only one trigger register replication, but the adjacent

	 * register is always read as zero, so there's no need to handle this

	 * case separately.

	 */

	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |

		irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));

	if (!(val & mask))

drivers/irqchip/irq-renesas-rzg2l.c

+14 −2
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 */



#include <linux/bitfield.h>

#include <linux/cleanup.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>
@@ -530,12 +531,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, 
static int rzg2l_irqc_common_init(struct device_node *node, struct device_node *parent,

				  const struct irq_chip *irq_chip)

{

	struct platform_device *pdev = of_find_device_by_node(node);

	struct device *dev __free(put_device) = pdev ? &pdev->dev : NULL;

	struct irq_domain *irq_domain, *parent_domain;

	struct platform_device *pdev;

	struct reset_control *resetn;

	int ret;



	pdev = of_find_device_by_node(node);

	if (!pdev)

		return -ENODEV;
@@ -591,6 +592,17 @@ static int rzg2l_irqc_common_init(struct device_node *node, struct device_node * 


	register_syscore_ops(&rzg2l_irqc_syscore_ops);



	/*

	 * Prevent the cleanup function from invoking put_device by assigning

	 * NULL to dev.

	 *

	 * make coccicheck will complain about missing put_device calls, but

	 * those are false positives, as dev will be automatically "put" via

	 * __free_put_device on the failing path.

	 * On the successful path we don't actually want to "put" dev.

	 */

	dev = NULL;



	return 0;



pm_put:

drivers/irqchip/irq-riscv-imsic-platform.c

+1 −1
Original line number Diff line number Diff line
@@ -341,7 +341,7 @@ int imsic_irqdomain_init(void) 
		imsic->fwnode, global->hart_index_bits, global->guest_index_bits);

	pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n",

		imsic->fwnode, global->group_index_bits, global->group_index_shift);

	pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n",

	pr_info("%pfwP: per-CPU IDs %d at base address %pa\n",

		imsic->fwnode, global->nr_ids, &global->base_addr);

	pr_info("%pfwP: total %d interrupts available\n",

		imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1));