Commit 94d904ae authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
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drm/amd/display: Allow Latency Increase For Last Strategy



[Why]
Playing 1080p video on 4k60 timing uses UCLK DPM5 and mode support
determines that p-state switching is not supported.

[How]
Allow DML to increase latency as the last strategy so strategies such
as VBlank p-state switching may become possible

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9afeda04
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+1 −0
Original line number Diff line number Diff line
@@ -1798,6 +1798,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp
	}

	if (s->pmo_dcn4.num_pstate_candidates > 0) {
		s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates - 1].allow_state_increase = true;
		s->pmo_dcn4.cur_pstate_candidate = -1;
		return true;
	} else {