Commit 95265e4b authored by Chris Park's avatar Chris Park Committed by Alex Deucher
Browse files

drm/amd/display: Block Invalid TMDS operation 



[Why]
When sink type is TMDS, PHY programming does not block against pixel
clock greater than 600MHz.

[How]
Based on sink type, block greater than 600MHz phy programming.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Signed-off-by: default avatarChris Park <chris.park@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f9dfa31f

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+3 −0
Original line number Diff line number Diff line
@@ -1105,6 +1105,9 @@ static bool dcn401_program_pix_clk( 
				&dto_params);



	} else {

		if (pll_settings->actual_pix_clk_100hz > 6000000UL)

			return false;



		/* disables DP DTO when provided with TMDS signal type */

		clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

				clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+4 −0
Original line number Diff line number Diff line
@@ -1953,6 +1953,10 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 
		stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;

	if (stream->phy_pix_clk > 340000)

		is_over_340mhz = true;

	if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) {

		ASSERT(false);

		return;

	}



	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

		unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &