Commit 954b38fd authored by Timur Tabi's avatar Timur Tabi Committed by Alexandre Courbot
Browse files

gpu: nova-core: Add basic Turing HAL 



Add the basic HAL for recognizing Turing GPUs.  This isn't enough
to support booting GSP-RM on Turing, but it's a start.

Note that GA100, which boots using the same method as Turing, is not
supported yet.

Signed-off-by: default avatarTimur Tabi <ttabi@nvidia.com>
Reviewed-by: default avatarJohn Hubbard <jhubbard@nvidia.com>
Reviewed-by: default avatarGary Guo <gary@garyguo.net>
Acked-by: default avatarDanilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260122222848.2555890-8-ttabi@nvidia.com


Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
parent 82ed3243

drivers/gpu/nova-core/falcon/hal.rs

+4 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
};



mod ga102;

mod tu102;



/// Hardware Abstraction Layer for Falcon cores.

///
@@ -60,6 +61,9 @@ pub(super) fn falcon_hal<E: FalconEngine + 'static>( 
    use Chipset::*;



    let hal = match chipset {

        TU102 | TU104 | TU106 | TU116 | TU117 => {

            KBox::new(tu102::Tu102::<E>::new(), GFP_KERNEL)? as KBox<dyn FalconHal<E>>

        }

        GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => {

            KBox::new(ga102::Ga102::<E>::new(), GFP_KERNEL)? as KBox<dyn FalconHal<E>>

        }

drivers/gpu/nova-core/falcon/hal/tu102.rs

0 → 100644
+79 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



use core::marker::PhantomData;



use kernel::{

    io::poll::read_poll_timeout,

    prelude::*,

    time::delay::fsleep,

    time::Delta, //

};



use crate::{

    driver::Bar0,

    falcon::{

        Falcon,

        FalconBromParams,

        FalconEngine, //

    },

    regs, //

};



use super::FalconHal;



pub(super) struct Tu102<E: FalconEngine>(PhantomData<E>);



impl<E: FalconEngine> Tu102<E> {

    pub(super) fn new() -> Self {

        Self(PhantomData)

    }

}



impl<E: FalconEngine> FalconHal<E> for Tu102<E> {

    fn select_core(&self, _falcon: &Falcon<E>, _bar: &Bar0) -> Result {

        Ok(())

    }



    fn signature_reg_fuse_version(

        &self,

        _falcon: &Falcon<E>,

        _bar: &Bar0,

        _engine_id_mask: u16,

        _ucode_id: u8,

    ) -> Result<u32> {

        Ok(0)

    }



    fn program_brom(&self, _falcon: &Falcon<E>, _bar: &Bar0, _params: &FalconBromParams) -> Result {

        Ok(())

    }



    fn is_riscv_active(&self, bar: &Bar0) -> bool {

        let cpuctl = regs::NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS::read(bar, &E::ID);

        cpuctl.active_stat()

    }



    fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result {

        // TIMEOUT: memory scrubbing should complete in less than 10ms.

        read_poll_timeout(

            || Ok(regs::NV_PFALCON_FALCON_DMACTL::read(bar, &E::ID)),

            |r| r.mem_scrubbing_done(),

            Delta::ZERO,

            Delta::from_millis(10),

        )

        .map(|_| ())

    }



    fn reset_eng(&self, bar: &Bar0) -> Result {

        regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(true));



        // TIMEOUT: falcon engine should not take more than 10us to reset.

        fsleep(Delta::from_micros(10));



        regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(false));



        self.reset_wait_mem_scrubbing(bar)?;



        Ok(())

    }

}

drivers/gpu/nova-core/regs.rs

+14 −0
Original line number Diff line number Diff line
@@ -307,6 +307,13 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 
    7:7     secure_stat as bool;

});



impl NV_PFALCON_FALCON_DMACTL {

    /// Returns `true` if memory scrubbing is completed.

    pub(crate) fn mem_scrubbing_done(self) -> bool {

        !self.dmem_scrubbing() && !self.imem_scrubbing()

    }

}



register!(NV_PFALCON_FALCON_DMATRFBASE @ PFalconBase[0x00000110] {

    31:0    base as u32;

});
@@ -389,6 +396,13 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 


// PRISCV



// RISC-V status register for debug (Turing and GA100 only).

// Reflects current RISC-V core status.

register!(NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS @ PFalcon2Base[0x00000240] {

    0:0     active_stat as bool, "RISC-V core active/inactive status";

});



// GA102 and later

register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] {

    0:0     halted as bool;

    7:7     active_stat as bool;