Commit 95587ecf authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-evk: correct vbus pad settings 



According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Not set reserved bit.

Fixes: 9e847693 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e6e1bc0e

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+15 −15
Original line number Diff line number Diff line
@@ -415,21 +415,21 @@ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 


	pinctrl_fec: fecgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3

			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f

			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2

			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16

			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10

		>;

	};