Commit 9563c343 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/mediatek' 

- Convert DT binding to YAML schema (Christian Marangi)

- Add Airoha AN7583 DT compatible and driver support (Christian Marangi)

* pci/controller/mediatek:
  PCI: mediatek: Add support for Airoha AN7583 SoC
  PCI: mediatek: Use generic MACRO for TPVPERL delay
  PCI: mediatek: Convert bool to single quirks entry and bitmap
  dt-bindings: PCI: mediatek: Add support for Airoha AN7583
  dt-bindings: PCI: mediatek: Convert to YAML schema
parents 5606b7ba 09150ab1

Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PCIe controller on MediaTek SoCs



maintainers:

  - Christian Marangi <ansuelsmth@gmail.com>



properties:

  compatible:

    enum:

      - mediatek,mt2701-pcie

      - mediatek,mt7623-pcie



  reg:

    minItems: 4

    maxItems: 4



  reg-names:

    items:

      - const: subsys

      - const: port0

      - const: port1

      - const: port2



  clocks:

    minItems: 4

    maxItems: 4



  clock-names:

    items:

      - const: free_ck

      - const: sys_ck0

      - const: sys_ck1

      - const: sys_ck2



  resets:

    minItems: 3

    maxItems: 3



  reset-names:

    items:

      - const: pcie-rst0

      - const: pcie-rst1

      - const: pcie-rst2



  phys:

    minItems: 3

    maxItems: 3



  phy-names:

    items:

      - const: pcie-phy0

      - const: pcie-phy1

      - const: pcie-phy2



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - ranges

  - clocks

  - clock-names

  - '#interrupt-cells'

  - resets

  - reset-names

  - phys

  - phy-names

  - power-domains

  - pcie@0,0

  - pcie@1,0

  - pcie@2,0



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#



unevaluatedProperties: false



examples:

  # MT7623

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/mt2701-clk.h>

    #include <dt-bindings/reset/mt2701-resets.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/power/mt2701-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@1a140000 {

            compatible = "mediatek,mt7623-pcie";

            device_type = "pci";

            reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */

                  <0 0x1a142000 0 0x1000>, /* Port0 registers */

                  <0 0x1a143000 0 0x1000>, /* Port1 registers */

                  <0 0x1a144000 0 0x1000>; /* Port2 registers */

            reg-names = "subsys", "port0", "port1", "port2";

            #address-cells = <3>;

            #size-cells = <2>;

            #interrupt-cells = <1>;

            interrupt-map-mask = <0xf800 0 0 0>;

            interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,

                            <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,

                            <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

            clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

                    <&hifsys CLK_HIFSYS_PCIE0>,

                    <&hifsys CLK_HIFSYS_PCIE1>,

                    <&hifsys CLK_HIFSYS_PCIE2>;

            clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";

            resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,

                     <&hifsys MT2701_HIFSYS_PCIE1_RST>,

                     <&hifsys MT2701_HIFSYS_PCIE2_RST>;

            reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";

            phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,

                   <&pcie2_phy PHY_TYPE_PCIE>;

            phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";

            power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

            bus-range = <0x00 0xff>;

            ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>,	/* I/O space */

                     <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */



            pcie@0,0 {

                device_type = "pci";

                reg = <0x0000 0 0 0 0>;

                #address-cells = <3>;

                #size-cells = <2>;

                #interrupt-cells = <1>;

                interrupt-map-mask = <0 0 0 0>;

                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;

                ranges;

            };



            pcie@1,0 {

                device_type = "pci";

                reg = <0x0800 0 0 0 0>;

                #address-cells = <3>;

                #size-cells = <2>;

                #interrupt-cells = <1>;

                interrupt-map-mask = <0 0 0 0>;

                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

                ranges;

            };



            pcie@2,0 {

                device_type = "pci";

                reg = <0x1000 0 0 0 0>;

                #address-cells = <3>;

                #size-cells = <2>;

                #interrupt-cells = <1>;

                interrupt-map-mask = <0 0 0 0>;

                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

                ranges;

            };

        };

    };

Documentation/devicetree/bindings/pci/mediatek-pcie.txt

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MediaTek Gen2 PCIe controller



Required properties:

- compatible: Should contain one of the following strings:

	"mediatek,mt2701-pcie"

	"mediatek,mt2712-pcie"

	"mediatek,mt7622-pcie"

	"mediatek,mt7623-pcie"

	"mediatek,mt7629-pcie"

	"airoha,en7523-pcie"

- device_type: Must be "pci"

- reg: Base addresses and lengths of the root ports.

- reg-names: Names of the above areas to use during resource lookup.

- #address-cells: Address representation for root ports (must be 3)

- #size-cells: Size representation for root ports (must be 2)

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names:

  Mandatory entries:

   - sys_ckN :transaction layer and data link layer clock

  Required entries for MT2701/MT7623:

   - free_ck :for reference clock of PCIe subsys

  Required entries for MT2712/MT7622:

   - ahb_ckN :AHB slave interface operating clock for CSR access and RC

	      initiated MMIO access

  Required entries for MT7622:

   - axi_ckN :application layer MMIO channel operating clock

   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when

	      pcie_mac_ck/pcie_pipe_ck is turned off

   - obff_ckN :OBFF functional block operating clock

   - pipe_ckN :LTSSM and PHY/MAC layer operating clock

  where N starting from 0 to one less than the number of root ports.

- phys: List of PHY specifiers (used by generic PHY framework).

- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the

  number of PHYs as specified in *phys* property.

- power-domains: A phandle and power domain specifier pair to the power domain

  which is responsible for collapsing and restoring power to the peripheral.

- bus-range: Range of bus numbers associated with this controller.

- ranges: Ranges for the PCI memory and I/O regions.



Required properties for MT7623/MT2701:

- #interrupt-cells: Size representation for interrupts (must be 1)

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the

  number of root ports.



Required properties for MT2712/MT7622/MT7629:

-interrupts: A list of interrupt outputs of the controller, must have one

	     entry for each PCIe port

- interrupt-names: Must include the following entries:

	- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received

- linux,pci-domain: PCI domain ID. Should be unique for each host controller



In addition, the device tree node must have sub-nodes describing each

PCIe port interface, having the following mandatory properties:



Required properties:

- device_type: Must be "pci"

- reg: Only the first four bytes are used to refer to the correct bus number

  and device number.

- #address-cells: Must be 3

- #size-cells: Must be 2

- #interrupt-cells: Must be 1

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- ranges: Sub-ranges distributed from the PCIe controller node. An empty

  property is sufficient.



Examples for MT7623:



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",

			     "mediatek,mt2701-hifsys",

			     "syscon";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pcie: pcie@1a140000 {

		compatible = "mediatek,mt7623-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */

		      <0 0x1a142000 0 0x1000>, /* Port0 registers */

		      <0 0x1a143000 0 0x1000>, /* Port1 registers */

		      <0 0x1a144000 0 0x1000>; /* Port2 registers */

		reg-names = "subsys", "port0", "port1", "port2";

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xf800 0 0 0>;

		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,

				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,

				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

			 <&hifsys CLK_HIFSYS_PCIE0>,

			 <&hifsys CLK_HIFSYS_PCIE1>,

			 <&hifsys CLK_HIFSYS_PCIE2>;

		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";

		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;

		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,

		       <&pcie2_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		bus-range = <0x00 0xff>;

		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000	/* I/O space */

			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */



		pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;

			ranges;

		};



		pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

			ranges;

		};



		pcie@2,0 {

			reg = <0x1000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

			ranges;

		};

	};



Examples for MT2712:



	pcie1: pcie@112ff000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x112ff000 0 0x1000>;

		reg-names = "port1";

		linux,pci-domain = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE1>;

		clock-names = "sys_ck1", "ahb_ck1";

		phys = <&u3port1 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy1";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;

		status = "disabled";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc1 0>,

				<0 0 0 2 &pcie_intc1 1>,

				<0 0 0 3 &pcie_intc1 2>,

				<0 0 0 4 &pcie_intc1 3>;

		pcie_intc1: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



	pcie0: pcie@11700000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x11700000 0 0x1000>;

		reg-names = "port0";

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&pericfg CLK_PERI_PCIE0>;

		clock-names = "sys_ck0", "ahb_ck0";

		phys = <&u3port0 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;

		status = "disabled";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc0 0>,

				<0 0 0 2 &pcie_intc0 1>,

				<0 0 0 3 &pcie_intc0 2>,

				<0 0 0 4 &pcie_intc0 3>;

		pcie_intc0: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



Examples for MT7622:



	pcie0: pcie@1a143000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";

		reg = <0 0x1a143000 0 0x1000>;

		reg-names = "port0";

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "pcie_irq";

		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,

			 <&pciesys CLK_PCIE_P0_AHB_EN>,

			 <&pciesys CLK_PCIE_P0_AUX_EN>,

			 <&pciesys CLK_PCIE_P0_AXI_EN>,

			 <&pciesys CLK_PCIE_P0_OBFF_EN>,

			 <&pciesys CLK_PCIE_P0_PIPE_EN>;

		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",

			      "axi_ck0", "obff_ck0", "pipe_ck0";



		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;

		status = "disabled";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc0 0>,

				<0 0 0 2 &pcie_intc0 1>,

				<0 0 0 3 &pcie_intc0 2>,

				<0 0 0 4 &pcie_intc0 3>;

		pcie_intc0: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



	pcie1: pcie@1a145000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";

		reg = <0 0x1a145000 0 0x1000>;

		reg-names = "port1";

		linux,pci-domain = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "pcie_irq";

		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,

			 /* designer has connect RC1 with p0_ahb clock */

			 <&pciesys CLK_PCIE_P0_AHB_EN>,

			 <&pciesys CLK_PCIE_P1_AUX_EN>,

			 <&pciesys CLK_PCIE_P1_AXI_EN>,

			 <&pciesys CLK_PCIE_P1_OBFF_EN>,

			 <&pciesys CLK_PCIE_P1_PIPE_EN>;

		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",

			      "axi_ck1", "obff_ck1", "pipe_ck1";



		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;

		status = "disabled";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc1 0>,

				<0 0 0 2 &pcie_intc1 1>,

				<0 0 0 3 &pcie_intc1 2>,

				<0 0 0 4 &pcie_intc1 3>;

		pcie_intc1: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};

Documentation/devicetree/bindings/pci/mediatek-pcie.yaml

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File added.

Preview size limit exceeded, changes collapsed.

drivers/pci/controller/pcie-mediatek.c

+81 −32
Original line number Diff line number Diff line
@@ -142,24 +142,34 @@ 


struct mtk_pcie_port;



/**

 * enum mtk_pcie_quirks - MTK PCIe quirks

 * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed

 * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed

 * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block

 * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe

 */

enum mtk_pcie_quirks {

	MTK_PCIE_FIX_CLASS_ID = BIT(0),

	MTK_PCIE_FIX_DEVICE_ID = BIT(1),

	MTK_PCIE_NO_MSI = BIT(2),

	MTK_PCIE_SKIP_RSTB = BIT(3),

};



/**

 * struct mtk_pcie_soc - differentiate between host generations

 * @need_fix_class_id: whether this host's class ID needed to be fixed or not

 * @need_fix_device_id: whether this host's device ID needed to be fixed or not

 * @no_msi: Bridge has no MSI support, and relies on an external block

 * @device_id: device ID which this host need to be fixed

 * @ops: pointer to configuration access functions

 * @startup: pointer to controller setting functions

 * @setup_irq: pointer to initialize IRQ functions

 * @quirks: PCIe device quirks.

 */

struct mtk_pcie_soc {

	bool need_fix_class_id;

	bool need_fix_device_id;

	bool no_msi;

	unsigned int device_id;

	struct pci_ops *ops;

	int (*startup)(struct mtk_pcie_port *port);

	int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);

	enum mtk_pcie_quirks quirks;

};



/**
@@ -679,31 +689,28 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);

	}



	if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) {

		/* Assert all reset signals */

		writel(0, port->base + PCIE_RST_CTRL);



		/*

	 * Enable PCIe link down reset, if link status changed from link up to

	 * link down, this will reset MAC control registers and configuration

	 * space.

		 * Enable PCIe link down reset, if link status changed from

		 * link up to link down, this will reset MAC control registers

		 * and configuration space.

		 */

		writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);



	/*

	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and

	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should

	 * be delayed 100ms (TPVPERL) for the power and clock to become stable.

	 */

	msleep(100);

		msleep(PCIE_T_PVPERL_MS);



		/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/

		val = readl(port->base + PCIE_RST_CTRL);

		val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |

		       PCIE_MAC_SRSTB | PCIE_CRSTB;

		writel(val, port->base + PCIE_RST_CTRL);

	}



	/* Set up vendor ID and class code */

	if (soc->need_fix_class_id) {

	if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) {

		val = PCI_VENDOR_ID_MEDIATEK;

		writew(val, port->base + PCIE_CONF_VEND_ID);
@@ -711,7 +718,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
		writew(val, port->base + PCIE_CONF_CLASS_ID);

	}



	if (soc->need_fix_device_id)

	if (soc->quirks & MTK_PCIE_FIX_DEVICE_ID)

		writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);



	/* 100ms timeout value should be enough for Gen1/2 training */
@@ -821,6 +828,41 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 
	return 0;

}



static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port)

{

	struct mtk_pcie *pcie = port->pcie;

	struct device *dev = pcie->dev;

	struct pci_host_bridge *host;

	struct resource_entry *entry;

	struct regmap *pbus_regmap;

	resource_size_t addr;

	u32 args[2], size;



	/*

	 * Configure PBus base address and base address mask to allow

	 * the hw to detect if a given address is accessible on PCIe

	 * controller.

	 */

	pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,

							   "mediatek,pbus-csr",

							   ARRAY_SIZE(args),

							   args);

	if (IS_ERR(pbus_regmap))

		return PTR_ERR(pbus_regmap);



	host = pci_host_bridge_from_priv(pcie);

	entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);

	if (!entry)

		return -ENODEV;



	addr = entry->res->start - entry->offset;

	regmap_write(pbus_regmap, args[0], lower_32_bits(addr));

	size = lower_32_bits(resource_size(entry->res));

	regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));



	return mtk_pcie_startup_port_v2(port);

}



static void mtk_pcie_enable_port(struct mtk_pcie_port *port)

{

	struct mtk_pcie *pcie = port->pcie;
@@ -1099,7 +1141,7 @@ static int mtk_pcie_probe(struct platform_device *pdev) 


	host->ops = pcie->soc->ops;

	host->sysdata = pcie;

	host->msi_domain = pcie->soc->no_msi;

	host->msi_domain = !!(pcie->soc->quirks & MTK_PCIE_NO_MSI);



	err = pci_host_probe(host);

	if (err)
@@ -1187,9 +1229,9 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = { 
};



static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {

	.no_msi = true,

	.ops = &mtk_pcie_ops,

	.startup = mtk_pcie_startup_port,

	.quirks = MTK_PCIE_NO_MSI,

};



static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
@@ -1199,22 +1241,29 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 
};



static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {

	.need_fix_class_id = true,

	.ops = &mtk_pcie_ops_v2,

	.startup = mtk_pcie_startup_port_v2,

	.setup_irq = mtk_pcie_setup_irq,

	.quirks = MTK_PCIE_FIX_CLASS_ID,

};



static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = {

	.ops = &mtk_pcie_ops_v2,

	.startup = mtk_pcie_startup_port_an7583,

	.setup_irq = mtk_pcie_setup_irq,

	.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB,

};



static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {

	.need_fix_class_id = true,

	.need_fix_device_id = true,

	.device_id = PCI_DEVICE_ID_MEDIATEK_7629,

	.ops = &mtk_pcie_ops_v2,

	.startup = mtk_pcie_startup_port_v2,

	.setup_irq = mtk_pcie_setup_irq,

	.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID,

};



static const struct of_device_id mtk_pcie_ids[] = {

	{ .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 },

	{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },

	{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },

	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },