Commit 957eedc7 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.7

- Smstateen and Zicond support for Guest/VM
- Virtualized senvcfg CSR for Guest/VM
- Added Smstateen registers to the get-reg-list selftests
- Added Zicond to the get-reg-list selftests
- Virtualized SBI debug console (DBCN) for Guest/VM
- Added SBI debug console (DBCN) to the get-reg-list selftests
parents ef12ea62 d9c00f44

Documentation/devicetree/bindings/riscv/extensions.yaml

+12 −0
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@@ -128,6 +128,12 @@ properties: 
            changes to interrupts as frozen at commit ccbddab ("Merge pull

            request #42 from riscv/jhauser-2023-RC4") of riscv-aia.



        - const: smstateen

          description: |

            The standard Smstateen extension for controlling access to CSRs

            added by other RISC-V extensions in H/S/VS/U/VU modes and as

            ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.



        - const: ssaia

          description: |

            The standard Ssaia supervisor-level extension for the advanced
@@ -212,6 +218,12 @@ properties: 
            ratified in the 20191213 version of the unprivileged ISA

            specification.



        - const: zicond

          description:

            The standard Zicond extension for conditional arithmetic and

            conditional-select/move operations as ratified in commit 95cf1f9

            ("Add changes requested by Ved during signoff") of riscv-zicond.



        - const: zicsr

          description: |

            The standard Zicsr extension for control and status register

MAINTAINERS

+1 −0
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@@ -11570,6 +11570,7 @@ F: arch/riscv/include/asm/kvm* 
F:	arch/riscv/include/uapi/asm/kvm*

F:	arch/riscv/kvm/

F:	tools/testing/selftests/kvm/*/riscv/

F:	tools/testing/selftests/kvm/riscv/









KERNEL VIRTUAL MACHINE for s390 (KVM/s390)









M:	Christian Borntraeger <borntraeger@linux.ibm.com>
































arch/riscv/include/asm/csr.h



+18
−0






























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@@ -203,6 +203,18 @@







#define ENVCFG_CBIE_INV			_AC(0x3, UL)









#define ENVCFG_FIOM			_AC(0x1, UL)



















/* Smstateen bits */









#define SMSTATEEN0_AIA_IMSIC_SHIFT	58









#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)









#define SMSTATEEN0_AIA_SHIFT		59









#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)









#define SMSTATEEN0_AIA_ISEL_SHIFT	60









#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)









#define SMSTATEEN0_HSENVCFG_SHIFT	62









#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)









#define SMSTATEEN0_SSTATEEN0_SHIFT	63









#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)



















/* symbolic CSR names: */









#define CSR_CYCLE		0xc00









#define CSR_TIME		0xc01








@@ -275,6 +287,8 @@







#define CSR_SIE			0x104









#define CSR_STVEC		0x105









#define CSR_SCOUNTEREN		0x106









#define CSR_SENVCFG		0x10a









#define CSR_SSTATEEN0		0x10c









#define CSR_SSCRATCH		0x140









#define CSR_SEPC		0x141









#define CSR_SCAUSE		0x142








@@ -349,6 +363,10 @@







#define CSR_VSIEH		0x214









#define CSR_VSIPH		0x254



















/* Hypervisor stateen CSRs */









#define CSR_HSTATEEN0		0x60c









#define CSR_HSTATEEN0H		0x61c



















#define CSR_MSTATUS		0x300









#define CSR_MISA		0x301









#define CSR_MIDELEG		0x303
































arch/riscv/include/asm/hwcap.h



+2
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@@ -58,6 +58,8 @@







#define RISCV_ISA_EXT_ZICSR		40









#define RISCV_ISA_EXT_ZIFENCEI		41









#define RISCV_ISA_EXT_ZIHPM		42









#define RISCV_ISA_EXT_SMSTATEEN		43









#define RISCV_ISA_EXT_ZICOND		44



















#define RISCV_ISA_EXT_MAX		64










































arch/riscv/include/asm/kvm_host.h



+18
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@@ -162,6 +162,16 @@ struct kvm_vcpu_csr {







	unsigned long hvip;









	unsigned long vsatp;









	unsigned long scounteren;









	unsigned long senvcfg;









};



















struct kvm_vcpu_config {









	u64 henvcfg;









	u64 hstateen0;









};



















struct kvm_vcpu_smstateen_csr {









	unsigned long sstateen0;









};



















struct kvm_vcpu_arch {








@@ -183,6 +193,8 @@ struct kvm_vcpu_arch {







	unsigned long host_sscratch;









	unsigned long host_stvec;









	unsigned long host_scounteren;









	unsigned long host_senvcfg;









	unsigned long host_sstateen0;



















	/* CPU context of Host */









	struct kvm_cpu_context host_context;








@@ -193,6 +205,9 @@ struct kvm_vcpu_arch {







	/* CPU CSR context of Guest VCPU */









	struct kvm_vcpu_csr guest_csr;



















	/* CPU Smstateen CSR context of Guest VCPU */









	struct kvm_vcpu_smstateen_csr smstateen_csr;



















	/* CPU context upon Guest VCPU reset */









	struct kvm_cpu_context guest_reset_context;


















@@ -244,6 +259,9 @@ struct kvm_vcpu_arch {

















	/* Performance monitoring context */









	struct kvm_pmu pmu_context;



















	/* 'static' configurations which are set only once */









	struct kvm_vcpu_config cfg;









};



















static inline void kvm_arch_sync_events(struct kvm *kvm) {}