Commit 9583f9d2 authored by Jim Quinlan's avatar Jim Quinlan Committed by Bjorn Helgaas
Browse files

PCI: brcmstb: Fix disabling L0s capability 



caab002d ("PCI: brcmstb: Disable L0s component of ASPM if requested")
set PCI_EXP_LNKCAP_ASPM_L1 and (optionally) PCI_EXP_LNKCAP_ASPM_L0S in
PCI_EXP_LNKCAP (aka PCIE_RC_CFG_PRIV1_LINK_CAPABILITY in brcmstb).

But instead of using PCI_EXP_LNKCAP_ASPM_L1 and PCI_EXP_LNKCAP_ASPM_L0S
directly, it used PCIE_LINK_STATE_L1 and PCIE_LINK_STATE_L0S, which are
Linux-created values that only coincidentally matched the PCIe spec.
b478e162 ("PCI/ASPM: Consolidate link state defines") later changed
them so they no longer matched the PCIe spec, so the bits ended up in the
wrong place in PCI_EXP_LNKCAP.

Use PCI_EXP_LNKCAP_ASPM_L0S to clear L0s support when there's an
'aspm-no-l0s' property.  Rely on brcmstb hardware to advertise L0s and/or
L1 support otherwise.

Fixes: caab002d ("PCI: brcmstb: Disable L0s component of ASPM if requested")
Reported-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Closes: https://lore.kernel.org/linux-pci/20250925194424.GA2197200@bhelgaas


Signed-off-by: default avatarJim Quinlan <james.quinlan@broadcom.com>
[mani: reworded subject and description, added closes tag and CCed stable]
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
[bhelgaas: commit log]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251003170436.1446030-1-james.quinlan@broadcom.com
parent 3a866087

drivers/pci/controller/pcie-brcmstb.c

+3 −7
Original line number Diff line number Diff line
@@ -48,7 +48,6 @@ 


#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY			0x04dc

#define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK	0x1f0

#define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK	0xc00



#define PCIE_RC_CFG_PRIV1_ROOT_CAP			0x4f8

#define  PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK	0xf8
@@ -1075,7 +1074,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) 
	void __iomem *base = pcie->base;

	struct pci_host_bridge *bridge;

	struct resource_entry *entry;

	u32 tmp, burst, aspm_support, num_lanes, num_lanes_cap;

	u32 tmp, burst, num_lanes, num_lanes_cap;

	u8 num_out_wins = 0;

	int num_inbound_wins = 0;

	int memc, ret;
@@ -1175,12 +1174,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) 




	/* Don't advertise L0s capability if 'aspm-no-l0s' */

	aspm_support = PCIE_LINK_STATE_L1;

	if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))

		aspm_support |= PCIE_LINK_STATE_L0S;

	tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);

	u32p_replace_bits(&tmp, aspm_support,

		PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);

	if (of_property_read_bool(pcie->np, "aspm-no-l0s"))

		tmp &= ~PCI_EXP_LNKCAP_ASPM_L0S;

	writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);



	/* 'tmp' still holds the contents of PRIV1_LINK_CAPABILITY */