Commit 95b3899b authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by Lucas De Marchi
Browse files

drm/xe/psmi: Add Wa_16023683509 



This WA ensures GuC will restore the media MCFG registers at C6
exit.

Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://lore.kernel.org/r/20250821-psmi-v5-5-34ab7550d3d8@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 29042df3

drivers/gpu/drm/xe/xe_guc.c

+3 −0
Original line number Diff line number Diff line
@@ -219,6 +219,9 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc) 
	if (XE_GT_WA(gt, 14018913170))

		flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;



	if (XE_GT_WA(gt, 16023683509))

		flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6;



	return flags;

}

drivers/gpu/drm/xe/xe_guc_fwif.h

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ struct guc_update_exec_queue_policy { 
#define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)

#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)

#define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6	BIT(22)

#define   GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6	BIT(25)



#define GUC_CTL_FEATURE			2

#define   GUC_CTL_ENABLE_SLPC		BIT(2)

drivers/gpu/drm/xe/xe_wa_oob.rules

+2 −0
Original line number Diff line number Diff line
@@ -72,6 +72,8 @@ no_media_l3 MEDIA_VERSION(3000) 
		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)

		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)

		MEDIA_VERSION(3002), FUNC(xe_rtp_match_psmi_enabled)

16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)

		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_psmi_enabled)



# SoC workaround - currently applies to all platforms with the following

# primary GT GMDID