Commit 95ba6820 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom: document the Milos Global Clock Controller 



Add bindings documentation for the Milos (e.g. SM7635) Global Clock
Controller.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent b21b5b3a

Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on Milos



maintainers:

  - Luca Weiss <luca.weiss@fairphone.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on Milos.



  See also: include/dt-bindings/clock/qcom,milos-gcc.h



properties:

  compatible:

    const: qcom,milos-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

        compatible = "qcom,milos-gcc";

        reg = <0x00100000 0x1f4200>;

        clocks = <&rpmhcc RPMH_CXO_CLK>,

                 <&sleep_clk>,

                 <&pcie0_phy>,

                 <&pcie1_phy>,

                 <&ufs_mem_phy 0>,

                 <&ufs_mem_phy 1>,

                 <&ufs_mem_phy 2>,

                 <&usb_1_qmpphy>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;

    };



...

include/dt-bindings/clock/qcom,milos-gcc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H

#define _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H



/* GCC clocks */

#define GCC_GPLL0						0

#define GCC_GPLL0_OUT_EVEN					1

#define GCC_GPLL2						2

#define GCC_GPLL4						3

#define GCC_GPLL6						4

#define GCC_GPLL7						5

#define GCC_GPLL9						6

#define GCC_AGGRE_NOC_PCIE_AXI_CLK				7

#define GCC_AGGRE_UFS_PHY_AXI_CLK				8

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			9

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				10

#define GCC_BOOT_ROM_AHB_CLK					11

#define GCC_CAMERA_AHB_CLK					12

#define GCC_CAMERA_HF_AXI_CLK					13

#define GCC_CAMERA_HF_XO_CLK					14

#define GCC_CAMERA_SF_AXI_CLK					15

#define GCC_CAMERA_SF_XO_CLK					16

#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				17

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				18

#define GCC_CNOC_PCIE_SF_AXI_CLK				19

#define GCC_DDRSS_GPU_AXI_CLK					20

#define GCC_DDRSS_PCIE_SF_QTB_CLK				21

#define GCC_DISP_AHB_CLK					22

#define GCC_DISP_GPLL0_DIV_CLK_SRC				23

#define GCC_DISP_HF_AXI_CLK					24

#define GCC_DISP_XO_CLK						25

#define GCC_GP1_CLK						26

#define GCC_GP1_CLK_SRC						27

#define GCC_GP2_CLK						28

#define GCC_GP2_CLK_SRC						29

#define GCC_GP3_CLK						30

#define GCC_GP3_CLK_SRC						31

#define GCC_GPU_CFG_AHB_CLK					32

#define GCC_GPU_GPLL0_CLK_SRC					33

#define GCC_GPU_GPLL0_DIV_CLK_SRC				34

#define GCC_GPU_MEMNOC_GFX_CLK					35

#define GCC_GPU_SNOC_DVM_GFX_CLK				36

#define GCC_PCIE_0_AUX_CLK					37

#define GCC_PCIE_0_AUX_CLK_SRC					38

#define GCC_PCIE_0_CFG_AHB_CLK					39

#define GCC_PCIE_0_MSTR_AXI_CLK					40

#define GCC_PCIE_0_PHY_RCHNG_CLK				41

#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				42

#define GCC_PCIE_0_PIPE_CLK					43

#define GCC_PCIE_0_PIPE_CLK_SRC					44

#define GCC_PCIE_0_PIPE_DIV2_CLK				45

#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC				46

#define GCC_PCIE_0_SLV_AXI_CLK					47

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48

#define GCC_PCIE_1_AUX_CLK					49

#define GCC_PCIE_1_AUX_CLK_SRC					50

#define GCC_PCIE_1_CFG_AHB_CLK					51

#define GCC_PCIE_1_MSTR_AXI_CLK					52

#define GCC_PCIE_1_PHY_RCHNG_CLK				53

#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				54

#define GCC_PCIE_1_PIPE_CLK					55

#define GCC_PCIE_1_PIPE_CLK_SRC					56

#define GCC_PCIE_1_PIPE_DIV2_CLK				57

#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC				58

#define GCC_PCIE_1_SLV_AXI_CLK					59

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				60

#define GCC_PCIE_RSCC_CFG_AHB_CLK				61

#define GCC_PCIE_RSCC_XO_CLK					62

#define GCC_PDM2_CLK						63

#define GCC_PDM2_CLK_SRC					64

#define GCC_PDM_AHB_CLK						65

#define GCC_PDM_XO4_CLK						66

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				67

#define GCC_QMIP_CAMERA_RT_AHB_CLK				68

#define GCC_QMIP_DISP_AHB_CLK					69

#define GCC_QMIP_GPU_AHB_CLK					70

#define GCC_QMIP_PCIE_AHB_CLK					71

#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				72

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				73

#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				74

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				75

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				76

#define GCC_QUPV3_WRAP0_CORE_CLK				77

#define GCC_QUPV3_WRAP0_QSPI_REF_CLK				78

#define GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC			79

#define GCC_QUPV3_WRAP0_S0_CLK					80

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S1_CLK					82

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S2_CLK					84

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S3_CLK					86

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S4_CLK					88

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				89

#define GCC_QUPV3_WRAP0_S5_CLK					90

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				91

#define GCC_QUPV3_WRAP0_S6_CLK					92

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				93

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				94

#define GCC_QUPV3_WRAP1_CORE_CLK				95

#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				96

#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			97

#define GCC_QUPV3_WRAP1_S0_CLK					98

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S1_CLK					100

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S2_CLK					102

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S3_CLK					104

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S4_CLK					106

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				107

#define GCC_QUPV3_WRAP1_S5_CLK					108

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				109

#define GCC_QUPV3_WRAP1_S6_CLK					110

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				111

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				112

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				113

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				114

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				115

#define GCC_SDCC1_AHB_CLK					116

#define GCC_SDCC1_APPS_CLK					117

#define GCC_SDCC1_APPS_CLK_SRC					118

#define GCC_SDCC1_ICE_CORE_CLK					119

#define GCC_SDCC1_ICE_CORE_CLK_SRC				120

#define GCC_SDCC2_AHB_CLK					121

#define GCC_SDCC2_APPS_CLK					122

#define GCC_SDCC2_APPS_CLK_SRC					123

#define GCC_UFS_PHY_AHB_CLK					124

#define GCC_UFS_PHY_AXI_CLK					125

#define GCC_UFS_PHY_AXI_CLK_SRC					126

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				127

#define GCC_UFS_PHY_ICE_CORE_CLK				128

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				129

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				130

#define GCC_UFS_PHY_PHY_AUX_CLK					131

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				132

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				133

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				134

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				135

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				136

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				137

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				138

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				139

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				140

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				141

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			142

#define GCC_USB30_PRIM_ATB_CLK					143

#define GCC_USB30_PRIM_MASTER_CLK				144

#define GCC_USB30_PRIM_MASTER_CLK_SRC				145

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				146

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			147

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		148

#define GCC_USB30_PRIM_SLEEP_CLK				149

#define GCC_USB3_PRIM_PHY_AUX_CLK				150

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				151

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				152

#define GCC_USB3_PRIM_PHY_PIPE_CLK				153

#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				154

#define GCC_VIDEO_AHB_CLK					155

#define GCC_VIDEO_AXI0_CLK					156

#define GCC_VIDEO_XO_CLK					157



/* GCC resets */

#define GCC_CAMERA_BCR						0

#define GCC_DISPLAY_BCR						1

#define GCC_GPU_BCR						2

#define GCC_PCIE_0_BCR						3

#define GCC_PCIE_0_LINK_DOWN_BCR				4

#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5

#define GCC_PCIE_0_PHY_BCR					6

#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7

#define GCC_PCIE_1_BCR						8

#define GCC_PCIE_1_LINK_DOWN_BCR				9

#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10

#define GCC_PCIE_1_PHY_BCR					11

#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12

#define GCC_PCIE_RSCC_BCR					13

#define GCC_PDM_BCR						14

#define GCC_QUPV3_WRAPPER_0_BCR					15

#define GCC_QUPV3_WRAPPER_1_BCR					16

#define GCC_QUSB2PHY_PRIM_BCR					17

#define GCC_QUSB2PHY_SEC_BCR					18

#define GCC_SDCC1_BCR						19

#define GCC_SDCC2_BCR						20

#define GCC_UFS_PHY_BCR						21

#define GCC_USB30_PRIM_BCR					22

#define GCC_USB3_DP_PHY_PRIM_BCR				23

#define GCC_USB3_PHY_PRIM_BCR					24

#define GCC_USB3PHY_PHY_PRIM_BCR				25

#define GCC_VIDEO_AXI0_CLK_ARES					26

#define GCC_VIDEO_BCR						27



/* GCC power domains */

#define PCIE_0_GDSC						0

#define PCIE_0_PHY_GDSC						1

#define PCIE_1_GDSC						2

#define PCIE_1_PHY_GDSC						3

#define UFS_PHY_GDSC						4

#define UFS_MEM_PHY_GDSC					5

#define USB30_PRIM_GDSC						6

#define USB3_PHY_GDSC						7



#endif