Commit 95fe9e7e authored by Ulf Hansson's avatar Ulf Hansson
Browse files

pmdomain: Merge branch dt into next 



Merge the immutable branch dt into next, to allow the DT bindings to be
tested together with changes that are targeted for v6.9.

Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parents 841c3516 05d10395

Documentation/devicetree/bindings/power/qcom,rpmpd.yaml

+2 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ properties: 
          - qcom,msm8917-rpmpd

          - qcom,msm8939-rpmpd

          - qcom,msm8953-rpmpd

          - qcom,msm8974-rpmpd

          - qcom,msm8974pro-pma8084-rpmpd

          - qcom,msm8976-rpmpd

          - qcom,msm8994-rpmpd

          - qcom,msm8996-rpmpd

Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ properties: 
      - renesas,r8a779a0-sysc # R-Car V3U

      - renesas,r8a779f0-sysc # R-Car S4-8

      - renesas,r8a779g0-sysc # R-Car V4H

      - renesas,r8a779h0-sysc # R-Car V4M



  reg:

    maxItems: 1

Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml

+14 −8
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ properties: 
    const: 1



  power-domains:

    minItems: 8

    maxItems: 8

    minItems: 10

    maxItems: 10



  power-domain-names:

    items:
@@ -40,10 +40,12 @@ properties: 
      - const: trng

      - const: hdmi-tx

      - const: hdmi-tx-phy

      - const: hdcp

      - const: hrv



  clocks:

    minItems: 4

    maxItems: 4

    minItems: 5

    maxItems: 5



  clock-names:

    items:
@@ -51,6 +53,7 @@ properties: 
      - const: axi

      - const: ref_266m

      - const: ref_24m

      - const: fdcc



  interconnects:

    maxItems: 3
@@ -82,12 +85,15 @@ examples: 
        clocks = <&clk IMX8MP_CLK_HDMI_APB>,

                 <&clk IMX8MP_CLK_HDMI_ROOT>,

                 <&clk IMX8MP_CLK_HDMI_REF_266M>,

                 <&clk IMX8MP_CLK_HDMI_24M>;

        clock-names = "apb", "axi", "ref_266m", "ref_24m";

                 <&clk IMX8MP_CLK_HDMI_24M>,

                 <&clk IMX8MP_CLK_HDMI_FDCC_TST>;

        clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";

        power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,

                        <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,

                        <&pgc_hdmimix>, <&pgc_hdmi_phy>;

                        <&pgc_hdmimix>, <&pgc_hdmi_phy>,

                        <&pgc_hdmimix>, <&pgc_hdmimix>;

        power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",

                             "hdmi-tx", "hdmi-tx-phy";

                             "hdmi-tx", "hdmi-tx-phy",

                             "hdcp", "hrv";

        #power-domain-cells = <1>;

    };

include/dt-bindings/power/qcom-rpmpd.h

+7 −0
Original line number Diff line number Diff line
@@ -308,6 +308,13 @@ 
#define MSM8953_VDDMX		5

#define MSM8953_VDDMX_AO	6



/* MSM8974 Power Domain Indexes */

#define MSM8974_VDDCX		0

#define MSM8974_VDDCX_AO	1

#define MSM8974_VDDCX_VFC	2

#define MSM8974_VDDGFX		3

#define MSM8974_VDDGFX_VFC	4



/* MSM8976 Power Domain Indexes */

#define MSM8976_VDDCX		0

#define MSM8976_VDDCX_AO	1

include/dt-bindings/power/renesas,r8a779h0-sysc.h

0 → 100644
+49 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (C) 2023 Renesas Electronics Corp.

 */

#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__

#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__



/*

 * These power domain indices match the Power Domain Register Numbers (PDR)

 */



#define R8A779H0_PD_A1E0D0C0		0

#define R8A779H0_PD_A1E0D0C1		1

#define R8A779H0_PD_A1E0D0C2		2

#define R8A779H0_PD_A1E0D0C3		3

#define R8A779H0_PD_A2E0D0		16

#define R8A779H0_PD_A3CR0		21

#define R8A779H0_PD_A3CR1		22

#define R8A779H0_PD_A3CR2		23

#define R8A779H0_PD_A33DGA		24

#define R8A779H0_PD_A23DGB		25

#define R8A779H0_PD_C4			31

#define R8A779H0_PD_A1DSP0		33

#define R8A779H0_PD_A2IMP01		34

#define R8A779H0_PD_A2PSC		35

#define R8A779H0_PD_A2CV0		36

#define R8A779H0_PD_A2CV1		37

#define R8A779H0_PD_A3IMR0		38

#define R8A779H0_PD_A3IMR1		39

#define R8A779H0_PD_A3VC		40

#define R8A779H0_PD_A2CN0		42

#define R8A779H0_PD_A1CN0		44

#define R8A779H0_PD_A1DSP1		45

#define R8A779H0_PD_A2DMA		47

#define R8A779H0_PD_A2CV2		48

#define R8A779H0_PD_A2CV3		49

#define R8A779H0_PD_A3IMR2		50

#define R8A779H0_PD_A3IMR3		51

#define R8A779H0_PD_A3PCI		52

#define R8A779H0_PD_A2PCIPHY		53

#define R8A779H0_PD_A3VIP0		56

#define R8A779H0_PD_A3VIP2		58

#define R8A779H0_PD_A3ISP0		60

#define R8A779H0_PD_A3DUL		62



/* Always-on power area */

#define R8A779H0_PD_ALWAYS_ON		64



#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */