Commit 962ad087 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Add support for "input-schmitt-microvolt" property, as used in the
     Sophgo SoC

  New drivers:

   - Mobileye EyeQ5 pin controller, I think this is an automotive SoC

   - Rockchip rk3576 pin control support

   - Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000

  Improvements:

   - Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton and a
     few other drivers"

* tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (67 commits)
  pinctrl: intel: Constify struct intel_pinctrl parameter
  pinctrl: Remove redundant null pointer checks in pinctrl_remove_device_debugfs()
  pinctrl: baytrail: Drop duplicate return statement
  pinctrl: intel: Inline intel_gpio_community_irq_handler()
  dt-bindings: pinctrl: qcom: add missing type to GPIO hogs
  pinctrl: madera: Simplify with dev_err_probe()
  pinctrl: k210: Use devm_clk_get_enabled() helpers
  pinctrl: Join split messages and remove double whitespace
  pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
  pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
  pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
  pinctrl: mvebu: Fix devinit_dove_pinctrl_probe function
  pinctrl: sunxi: Use devm_clk_get_enabled() helpers
  pinctrl: sophgo: cv18xx: fix missed __iomem type identifier
  pinctrl: stmfx: Use string_choices API instead of ternary operator
  pinctrl: nomadik: Use kmemdup_array instead of kmemdup for multiple allocation
  pinctrl: intel: Introduce for_each_intel_gpio_group() helper et al.
  pinctrl: intel: Constify intel_get_community() returned object
  pinctrl: intel: Implement high impedance support
  pinctrl: intel: Add __intel_gpio_get_direction() helper
  ...
parents 5f153b63 264c1311

Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml

deleted100644 → 0
+0 −242
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobileye EyeQ5 pin controller



description: >

  The EyeQ5 pin controller handles the two pin banks of the system. It belongs

  to a system-controller block called OLB.



  Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin

  muxing supports two functions for each pin: first is GPIO, second is

  pin-dependent.



  Pins and groups are bijective.



maintainers:

  - Grégory Clement <gregory.clement@bootlin.com>

  - Théo Lebrun <theo.lebrun@bootlin.com>

  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>



$ref: pinctrl.yaml#



properties:

  compatible:

    enum:

      - mobileye,eyeq5-pinctrl



  reg:

    maxItems: 1



patternProperties:

  "-pins?$":

    type: object

    description: Pin muxing configuration.

    $ref: pinmux-node.yaml#

    additionalProperties: false

    properties:

      pins: true

      function:

        enum: [gpio,

               # Bank A

               timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,

               spi1, refclk0,

               # Bank B

               timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength: true

    required:

      - pins

      - function

    allOf:

      - if:

          properties:

            function:

              const: gpio

        then:

          properties:

            pins:

              items: # PA0 - PA28, PB0 - PB22

                pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'

      - if:

          properties:

            function:

              const: timer0

        then:

          properties:

            pins:

              items:

                enum: [PA0, PA1]

      - if:

          properties:

            function:

              const: timer1

        then:

          properties:

            pins:

              items:

                enum: [PA2, PA3]

      - if:

          properties:

            function:

              const: timer2

        then:

          properties:

            pins:

              items:

                enum: [PA4, PA5]

      - if:

          properties:

            function:

              const: timer5

        then:

          properties:

            pins:

              items:

                enum: [PA6, PA7, PA8, PA9]

      - if:

          properties:

            function:

              const: uart0

        then:

          properties:

            pins:

              items:

                enum: [PA10, PA11]

      - if:

          properties:

            function:

              const: uart1

        then:

          properties:

            pins:

              items:

                enum: [PA12, PA13]

      - if:

          properties:

            function:

              const: can0

        then:

          properties:

            pins:

              items:

                enum: [PA14, PA15]

      - if:

          properties:

            function:

              const: can1

        then:

          properties:

            pins:

              items:

                enum: [PA16, PA17]

      - if:

          properties:

            function:

              const: spi0

        then:

          properties:

            pins:

              items:

                enum: [PA18, PA19, PA20, PA21, PA22]

      - if:

          properties:

            function:

              const: spi1

        then:

          properties:

            pins:

              items:

                enum: [PA23, PA24, PA25, PA26, PA27]

      - if:

          properties:

            function:

              const: refclk0

        then:

          properties:

            pins:

              items:

                enum: [PA28]

      - if:

          properties:

            function:

              const: timer3

        then:

          properties:

            pins:

              items:

                enum: [PB0, PB1]

      - if:

          properties:

            function:

              const: timer4

        then:

          properties:

            pins:

              items:

                enum: [PB2, PB3]

      - if:

          properties:

            function:

              const: timer6

        then:

          properties:

            pins:

              items:

                enum: [PB4, PB5, PB6, PB7]

      - if:

          properties:

            function:

              const: uart2

        then:

          properties:

            pins:

              items:

                enum: [PB8, PB9]

      - if:

          properties:

            function:

              const: can2

        then:

          properties:

            pins:

              items:

                enum: [PB10, PB11]

      - if:

          properties:

            function:

              const: spi2

        then:

          properties:

            pins:

              items:

                enum: [PB12, PB13, PB14, PB15, PB16]

      - if:

          properties:

            function:

              const: spi3

        then:

          properties:

            pins:

              items:

                enum: [PB17, PB18, PB19, PB20, PB21]

      - if:

          properties:

            function:

              const: mclk0

        then:

          properties:

            pins:

              items:

                enum: [PB22]



required:

  - compatible

  - reg



additionalProperties: false

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml

+34 −36
Original line number Diff line number Diff line
@@ -71,51 +71,49 @@ patternProperties: 
          One or more groups of pins to mux to a certain function

        items:

          enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,

                  smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,

                  smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,

                  smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,

                  spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,

                  spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,

                  bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,

                  r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,

                  fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,

                  fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,

                  pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,

                  ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,

                  smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,

                  sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,

                  mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,

                  scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,

                  smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,

                  spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,

                  wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,

                  hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,

                  bu4b, bu5, bu5b, bu6, gpo187 ]

                  smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,

                  smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,

                  smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,

                  spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,

                  smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,

                  bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,

                  fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,

                  fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,

                  fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,

                  r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,

                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,

                  smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,

                  pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,

                  mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,

                  smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3, 

                  spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,

                  smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,

                  spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,

                  hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]



      function:

        description:

          The function that a group of pins is muxed to

        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,

                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,

                smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,

                smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,

                spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,

                spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,

                bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,

                r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,

                fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,

        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,

                smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,

                smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,

                smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,

                spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,

                uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,

                r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,

                fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,

                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,

                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,

                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,

                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,

                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,

                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,

                scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,

                smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,

                spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,

                wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,

                hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,

                bu4b, bu5, bu5b, bu6, gpo187 ]

                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,

                smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,

                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,

                smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,

                smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,

                hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,

                bu6, gpo187 ]



    dependencies:

      groups: [ function ]

Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml

+3 −0
Original line number Diff line number Diff line
@@ -96,6 +96,9 @@ properties: 
    type: boolean

    description: disable schmitt-trigger mode



  input-schmitt-microvolt:

    description: threshold strength for schmitt-trigger



  input-debounce:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: Takes the debounce time in usec as argument or 0 to disable

Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt

deleted100644 → 0
+0 −95
Original line number Diff line number Diff line 
Qualcomm APQ8064 TLMM block



Required properties:

- compatible: "qcom,apq8064-pinctrl"

- reg: Should be the base address and length of the TLMM block.

- interrupts: Should be the parent IRQ of the TLMM block.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be two.

- gpio-controller: Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.

- gpio-ranges: see ../gpio/gpio.txt



Optional properties:



- gpio-reserved-ranges: see ../gpio/gpio.txt



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



Qualcomm's pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.



The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.





The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:



 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,

 output-low, output-high.



Non-empty subnodes must specify the 'pins' property.



Valid values for pins are:

  gpio0-gpio89



Valid values for function are:

  cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,

  gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,

  gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,

  gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,

  gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,

  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold



Example:



	msmgpio: pinctrl@800000 {

		compatible = "qcom,apq8064-pinctrl";

		reg = <0x800000 0x4000>;



		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 16 0x4>;



		pinctrl-names = "default";

		pinctrl-0 = <&gsbi5_uart_default>;

		gpio-ranges = <&msmgpio 0 0 90>;



		gsbi5_uart_default: gsbi5_uart_default {

			mux {

				pins = "gpio51", "gpio52";

				function = "gsbi5";

			};



			tx {

				pins = "gpio51";

				drive-strength = <4>;

				bias-disable;

			};



			rx {

				pins = "gpio52";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};

Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml

0 → 100644
+110 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. APQ8064 TLMM block



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description: |

  Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC.



allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#



properties:

  compatible:

    const: qcom,apq8064-pinctrl



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  gpio-reserved-ranges: true



patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-apq8064-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-apq8064-tlmm-state"

        additionalProperties: false



$defs:

  qcom-apq8064-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    unevaluatedProperties: false



    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-8][0-9])$"

            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ]

        minItems: 1

        maxItems: 36



      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a,

                gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b,

                gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c,

                gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3,

                gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3,

                gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3,

                gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan,

                sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,

                ps_hold ]



    required:

      - pins



required:

  - compatible

  - reg



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@800000 {

        compatible = "qcom,apq8064-pinctrl";

        reg = <0x800000 0x4000>;



        gpio-controller;

        #gpio-cells = <2>;

        gpio-ranges = <&tlmm 0 0 90>;

        interrupt-controller;

        #interrupt-cells = <2>;

        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;



        uart-state {

            rx-pins {

                pins = "gpio52";

                function = "gsbi5";

                bias-pull-up;

            };



            tx-pins {

                pins = "gpio51";

                function = "gsbi5";

                bias-disable;

            };

        };

    };