Commit 962f1e79 authored by Dave Jiang's avatar Dave Jiang Committed by Bjorn Helgaas
Browse files

PCI/CXL: Move CXL Vendor ID to pci_ids.h 

Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL in
pci_ids.h in order to be utilized in PCI subsystem.

While the CXL Vendor ID (0x1e98) is not listed in the PCI SIG "Member
Companies" database at https://pcisig.com/membership/member-companies, the
SIG has confirmed that it is reserved by CXL.

Link: https://lore.kernel.org/r/20240502165851.1948523-2-dave.jiang@intel.com


Suggested-by: default avatarBjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/linux-cxl/20240402172323.GA1818777@bhelgaas/


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
[bhelgaas: update commit log]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 4cece764

drivers/cxl/core/pci.c

+3 −3
Original line number Diff line number Diff line
@@ -525,7 +525,7 @@ static int cxl_cdat_get_length(struct device *dev, 
	__le32 response[2];

	int rc;



	rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,

	rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,

		     CXL_DOE_PROTOCOL_TABLE_ACCESS,

		     &request, sizeof(request),

		     &response, sizeof(response));
@@ -555,7 +555,7 @@ static int cxl_cdat_read_table(struct device *dev, 
		__le32 request = CDAT_DOE_REQ(entry_handle);

		int rc;



		rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,

		rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,

			     CXL_DOE_PROTOCOL_TABLE_ACCESS,

			     &request, sizeof(request),

			     rsp, sizeof(*rsp) + remaining);
@@ -640,7 +640,7 @@ void read_cdat_data(struct cxl_port *port) 
	if (!pdev)

		return;



	doe_mb = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,

	doe_mb = pci_find_doe_mailbox(pdev, PCI_VENDOR_ID_CXL,

				      CXL_DOE_PROTOCOL_TABLE_ACCESS);

	if (!doe_mb) {

		dev_dbg(dev, "No CDAT mailbox\n");

drivers/cxl/core/regs.c

+1 −1
Original line number Diff line number Diff line
@@ -313,7 +313,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 
		.resource = CXL_RESOURCE_NONE,

	};



	regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,

	regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,

					   CXL_DVSEC_REG_LOCATOR);

	if (!regloc)

		return -ENXIO;

drivers/cxl/cxlpci.h

+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 
 * "DVSEC" redundancies removed. When obvious, abbreviations may be used.

 */

#define PCI_DVSEC_HEADER1_LENGTH_MASK	GENMASK(31, 20)

#define PCI_DVSEC_VENDOR_ID_CXL		0x1E98



/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */

#define CXL_DVSEC_PCIE_DEVICE					0

drivers/cxl/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -817,7 +817,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	cxlds->rcd = is_cxl_restricted(pdev);

	cxlds->serial = pci_get_dsn(pdev);

	cxlds->cxl_dvsec = pci_find_dvsec_capability(

		pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);

		pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);

	if (!cxlds->cxl_dvsec)

		dev_warn(&pdev->dev,

			 "Device DVSEC not present, skip CXL.mem init\n");

drivers/perf/cxl_pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ static ssize_t cxl_pmu_event_sysfs_show(struct device *dev, 


/* For CXL spec defined events */

#define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk)			\

	CXL_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)

	CXL_PMU_EVENT_ATTR(_name, PCI_VENDOR_ID_CXL, _gid, _msk)



static struct attribute *cxl_pmu_event_attrs[] = {

	CXL_PMU_EVENT_CXL_ATTR(clock_ticks,			CXL_PMU_GID_CLOCK_TICKS, BIT(0)),