Commit 96c47197 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: Add gpu support 



Add the necessary dt nodes for gpu support in sc7280.

Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1628691835-36958-1-git-send-email-akhilpo@codeaurora.org
parent c8efde9f

arch/arm64/boot/dts/qcom/sc7280.dtsi

+115 −0
Original line number Diff line number Diff line
@@ -686,6 +686,85 @@ lpass_ag_noc: interconnect@3c40000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		gpu@3d00000 {

			compatible = "qcom,adreno-635.0", "qcom,adreno";

			#stream-id-cells = <16>;

			reg = <0 0x03d00000 0 0x40000>,

			      <0 0x03d9e000 0 0x1000>,

			      <0 0x03d61000 0 0x800>;

			reg-names = "kgsl_3d0_reg_memory",

				    "cx_mem",

				    "cx_dbgc";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			iommus = <&adreno_smmu 0 0x401>;

			operating-points-v2 = <&gpu_opp_table>;

			qcom,gmu = <&gmu>;

			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;

			interconnect-names = "gfx-mem";



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-315000000 {

					opp-hz = /bits/ 64 <315000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-peak-kBps = <1804000>;

				};



				opp-450000000 {

					opp-hz = /bits/ 64 <450000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-peak-kBps = <4068000>;

				};



				opp-550000000 {

					opp-hz = /bits/ 64 <550000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-peak-kBps = <6832000>;

				};

			};

		};



		gmu: gmu@3d69000 {

			compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";

			reg = <0 0x03d6a000 0 0x34000>,

				<0 0x3de0000 0 0x10000>,

				<0 0x0b290000 0 0x10000>;

			reg-names = "gmu", "rscc", "gmu_pdc";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hfi", "gmu";

			clocks = <&gpucc 5>,

					<&gpucc 8>,

					<&gcc GCC_DDRSS_GPU_AXI_CLK>,

					<&gcc GCC_GPU_MEMNOC_GFX_CLK>,

					<&gpucc 2>,

					<&gpucc 15>,

					<&gpucc 11>;

			clock-names = "gmu",

				      "cxo",

				      "axi",

				      "memnoc",

				      "ahb",

				      "hub",

				      "smmu_vote";

			power-domains = <&gpucc 0>,

					<&gpucc 1>;

			power-domain-names = "cx",

					     "gx";

			iommus = <&adreno_smmu 5 0x400>;

			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				};

			};

		};



		gpucc: clock-controller@3d90000 {

			compatible = "qcom,sc7280-gpucc";

			reg = <0 0x03d90000 0 0x9000>;
@@ -700,6 +779,42 @@ gpucc: clock-controller@3d90000 { 
			#power-domain-cells = <1>;

		};



		adreno_smmu: iommu@3da0000 {

			compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";

			reg = <0 0x03da0000 0 0x20000>;

			#iommu-cells = <2>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

					<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

					<&gpucc 2>,

					<&gpucc 11>,

					<&gpucc 5>,

					<&gpucc 15>,

					<&gpucc 13>;

			clock-names = "gcc_gpu_memnoc_gfx_clk",

					"gcc_gpu_snoc_dvm_gfx_clk",

					"gpu_cc_ahb_clk",

					"gpu_cc_hlos1_vote_gpu_smmu_clk",

					"gpu_cc_cx_gmu_clk",

					"gpu_cc_hub_cx_int_clk",

					"gpu_cc_hub_aon_clk";



			power-domains = <&gpucc 0>;

		};



		stm@6002000 {

			compatible = "arm,coresight-stm", "arm,primecell";

			reg = <0 0x06002000 0 0x1000>,