Commit 96c79fef authored by Christophe Leroy's avatar Christophe Leroy Committed by Madhavan Srinivasan
Browse files

powerpc/8xx: Remove offset in SPRN_M_TWB 



SPRN_M_TWB contains the address of task PGD minus an offset which
compensates the offset required when accessing the kernel PGDIR.
However, since commit ac9f97ff ("powerpc/8xx: Inconditionally use
task PGDIR in DTLB misses") and commit 33c52752 ("powerpc/8xx:
Inconditionally use task PGDIR in ITLB misses") kernel PGDIR is not
used anymore in hot paths.

Remove this offset which was added by
commit fde5a905 ("powerpc/8xx: Optimise access to swapper_pg_dir")

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
[maddy: Fixed checkpatch.pl warning for "pathes"]
Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/9710d960b512996e64beebfd368cfeaadb28b3ba.1755509047.git.christophe.leroy@csgroup.eu
parent a41de5cc

arch/powerpc/kernel/head_8xx.S

+9 −7
Original line number Diff line number Diff line
@@ -190,7 +190,7 @@ instruction_counter: 
	INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)

	mtspr	SPRN_MD_EPN, r10

	mfspr	r10, SPRN_M_TWB	/* Get level 1 table */

	lwz	r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10)	/* Get level 1 entry */

	lwz	r11, 0(r10)	/* Get level 1 entry */

	mtspr	SPRN_MD_TWC, r11

	mfspr	r10, SPRN_MD_TWC

	lwz	r10, 0(r10)	/* Get the pte */
@@ -233,7 +233,7 @@ instruction_counter: 
	 */

	mfspr	r10, SPRN_MD_EPN

	mfspr	r10, SPRN_M_TWB	/* Get level 1 table */

	lwz	r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10)	/* Get level 1 entry */

	lwz	r11, 0(r10)	/* Get level 1 entry */



	mtspr	SPRN_MD_TWC, r11

	mfspr	r10, SPRN_MD_TWC
@@ -375,7 +375,7 @@ FixupPGD: 
	mfspr	r10, SPRN_DAR

	mtspr	SPRN_MD_EPN, r10

	mfspr	r11, SPRN_M_TWB	/* Get level 1 table */

	lwz	r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11)	/* Get the level 1 entry */

	lwz	r10, 0(r11)	/* Get the level 1 entry */

	cmpwi	cr1, r10, 0

	bne	cr1, 1f
@@ -384,7 +384,7 @@ FixupPGD: 
	lwz	r10, (swapper_pg_dir - PAGE_OFFSET)@l(r10)	/* Get the level 1 entry */

	cmpwi	cr1, r10, 0

	beq	cr1, 1f

	stw	r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11)	/* Set the level 1 entry */

	stw	r10, 0(r11)	/* Set the level 1 entry */

	mfspr	r10, SPRN_M_TW

	mtcr	r10

	mfspr	r10, SPRN_SPRG_SCRATCH0
@@ -412,9 +412,10 @@ FixupDAR:/* Entry point for dcbx workaround. */ 
	tophys(r11, r10)

	mfspr	r11, SPRN_M_TWB	/* Get level 1 table */

	rlwinm	r11, r11, 0, 20, 31

	oris	r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha

	oris	r11, r11, (swapper_pg_dir - PAGE_OFFSET)@h

	ori	r11, r11, (swapper_pg_dir - PAGE_OFFSET)@l

3:

	lwz	r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)	/* Get the level 1 entry */

	lwz	r11, 0(r11)	/* Get the level 1 entry */

	rlwinm	r11, r11, 0, ~_PMD_PAGE_8M

	mtspr	SPRN_MD_TWC, r11

	mfspr	r11, SPRN_MD_TWC
@@ -535,7 +536,8 @@ start_here: 
	li	r0,0

	stwu	r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)



	lis	r6, swapper_pg_dir@ha

	lis	r6, swapper_pg_dir@h

	ori	r6, r6, swapper_pg_dir@l

	tophys(r6,r6)

	mtspr	SPRN_M_TWB, r6

arch/powerpc/mm/nohash/mmu_context.c

+1 −9
Original line number Diff line number Diff line
@@ -203,15 +203,7 @@ static unsigned int steal_context_up(unsigned int id) 
static void set_context(unsigned long id, pgd_t *pgd)

{

	if (IS_ENABLED(CONFIG_PPC_8xx)) {

		s16 offset = (s16)(__pa(swapper_pg_dir));



		/*

		 * Register M_TWB will contain base address of level 1 table minus the

		 * lower part of the kernel PGDIR base address, so that all accesses to

		 * level 1 table are done relative to lower part of kernel PGDIR base

		 * address.

		 */

		mtspr(SPRN_M_TWB, __pa(pgd) - offset);

		mtspr(SPRN_M_TWB, __pa(pgd));



		/* Update context */

		mtspr(SPRN_M_CASID, id - 1);