Unverified Commit 96dd187c authored by Mark Brown's avatar Mark Brown
Browse files

This is continued work on Samsung S9(SM-9600) 

Merge series from Dzmitry Sankouski <dsankouski@gmail.com>:

Contains starqltechn device tree changes.
- sound (headphones and mics only)
parents a23ff143 e27c1250

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -19149,6 +19149,7 @@ F: Documentation/devicetree/bindings/soc/qcom/qcom,apr* 
F:	Documentation/devicetree/bindings/sound/qcom,*

F:	drivers/soc/qcom/apr.c

F:	include/dt-bindings/sound/qcom,wcd9335.h

F:	include/dt-bindings/sound/qcom,wcd934x.h

F:	sound/soc/codecs/lpass-rx-macro.*

F:	sound/soc/codecs/lpass-tx-macro.*

F:	sound/soc/codecs/lpass-va-macro.c

include/dt-bindings/sound/qcom,wcd934x.h

0 → 100644
+16 −0
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */



#ifndef __DT_SOUND_QCOM_WCD934x_H

#define __DT_SOUND_QCOM_WCD934x_H



#define AIF1_PB                 0

#define AIF1_CAP                1

#define AIF2_PB                 2

#define AIF2_CAP                3

#define AIF3_PB                 4

#define AIF3_CAP                5

#define AIF4_PB                 6

#define AIF4_VIFEED             7

#define AIF4_MAD_TX             8



#endif

sound/soc/codecs/wcd934x.c

+3 −13
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 
#include "wcd-clsh-v2.h"

#include "wcd-mbhc-v2.h"



#include <dt-bindings/sound/qcom,wcd934x.h>



#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\

			    SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\

			    SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
@@ -307,6 +309,7 @@ 
	{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}



#define WCD934X_MAX_MICBIAS	MIC_BIAS_4

#define NUM_CODEC_DAIS          9



enum {

	SIDO_SOURCE_INTERNAL,
@@ -434,19 +437,6 @@ enum { 
	COMPANDER_MAX,

};



enum {

	AIF1_PB = 0,

	AIF1_CAP,

	AIF2_PB,

	AIF2_CAP,

	AIF3_PB,

	AIF3_CAP,

	AIF4_PB,

	AIF4_VIFEED,

	AIF4_MAD_TX,

	NUM_CODEC_DAIS,

};



enum {

	INTn_1_INP_SEL_ZERO = 0,

	INTn_1_INP_SEL_DEC0,