Commit 96e1c895 authored by Simon Horman's avatar Simon Horman Committed by Jakub Kicinski
Browse files

net: stmmac: spelling corrections



Correct spelling as flagged by codespell.

Signed-off-by: default avatarSimon Horman <horms@kernel.org>
Reviewed-by: default avatarJoe Damato <joe@dama.to>
Link: https://patch.msgid.link/20260129-stmmac-spell-v1-1-c7df9a96e482@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 43dc088c
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+2 −2
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@@ -270,9 +270,9 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
	if (of_machine_is_compatible("fsl,imx8mp") ||
	    of_machine_is_compatible("fsl,imx91") ||
	    of_machine_is_compatible("fsl,imx93")) {
		/* Binding doc describes the propety:
		/* Binding doc describes the property:
		 * is required by i.MX8MP, i.MX91, i.MX93.
		 * is optinoal for i.MX8DXL.
		 * is optional for i.MX8DXL.
		 */
		dwmac->intf_regmap =
			syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,
+2 −2
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@@ -746,7 +746,7 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
	v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
	writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);

	/* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
	/* The timeout was previously set to 10ms, but some board (OrangePI0)
	 * need more if no cable plugged. 100ms seems OK
	 */
	err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
@@ -821,7 +821,7 @@ static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
		return ret;
	}

	/* Make sure the EPHY is properly reseted, as U-Boot may leave
	/* Make sure the EPHY is properly reset, as U-Boot may leave
	 * it at deasserted state, and thus it may fail to reset EMAC.
	 *
	 * This assumes the driver has exclusive access to the EPHY reset.
+1 −1
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@@ -152,7 +152,7 @@ enum inter_frame_gap {

/*--- DMA BLOCK defines ---*/
/* DMA Bus Mode register defines */
/* Programmable burst length (passed thorugh platform)*/
/* Programmable burst length (passed through platform)*/
#define DMA_BUS_MODE_PBL_MASK	GENMASK(13, 8)	/* Programmable Burst Len */
#define DMA_BUS_MODE_ATDS	0x00000080	/* Alternate Descriptor Size */

+1 −1
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@@ -108,7 +108,7 @@ static void dwmac100_set_filter(struct mac_device_info *hw,
		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the contens of the hash table
			 * index the contents of the hash table
			 */
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
			/* The most significant bit determines the register to
+1 −1
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@@ -88,7 +88,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)

	/* bits 5 7 0 | Frame status
	 * ----------------------------------------------------------
	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octets)
	 *      1 0 0 | IPv4/6 No CSUM errorS.
	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
	 *      1 1 0 | IPv4/6 CSUM IP HR error
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