Commit 96f0b56c authored by Jesse.zhang@amd.com's avatar Jesse.zhang@amd.com Committed by Alex Deucher
Browse files

drm/amdgpu: Add sysfs interface for jpeg reset mask 



Add the sysfs interface for jpeg:
jpeg_reset_mask

The interface is read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.

V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
    and print the strings in the order they are applied (Christian)

    check amdgpu_gpu_recovery  before creating sysfs file itself,
    and initialize supported_reset_types in IP version files (Lijo)

Signed-off-by: default avatarJesse Zhang <Jesse.Zhang@amd.com>
Suggested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarTim Huang <tim.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ea02ea94

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

+35 −0
Original line number Diff line number Diff line
@@ -415,3 +415,38 @@ void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev) 
			    &amdgpu_debugfs_jpeg_sched_mask_fops);

#endif

}



static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,

						struct device_attribute *attr,

						char *buf)

{

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(ddev);



	if (!adev)

		return -ENODEV;



	return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset);

}



static DEVICE_ATTR(jpeg_reset_mask, 0444,

		   amdgpu_get_jpeg_reset_mask, NULL);



int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)

{

	int r = 0;



	if (adev->jpeg.num_jpeg_inst) {

		r = device_create_file(adev->dev, &dev_attr_jpeg_reset_mask);

		if (r)

			return r;

	}



	return r;

}



void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)

{

	if (adev->jpeg.num_jpeg_inst)

		device_remove_file(adev->dev, &dev_attr_jpeg_reset_mask);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

+3 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ struct amdgpu_jpeg { 
	uint16_t inst_mask;

	uint8_t num_inst_per_aid;

	bool	indirect_sram;

	uint32_t supported_reset;

};



int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
@@ -150,5 +151,7 @@ int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev); 
int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,

			       enum AMDGPU_UCODE_ID ucode_id);

void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);

int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev);

void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev);



#endif /*__AMDGPU_JPEG_H__*/

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

+7 −0
Original line number Diff line number Diff line
@@ -121,6 +121,12 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 
	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);



	r = amdgpu_jpeg_ras_sw_init(adev);

	if (r)

		return r;

	/* TODO: Add queue reset mask when FW fully supports it */

	adev->jpeg.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);

	if (r)

		return r;
@@ -143,6 +149,7 @@ static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	amdgpu_jpeg_sysfs_reset_mask_fini(adev);

	r = amdgpu_jpeg_sw_fini(adev);



	return r;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

+8 −0
Original line number Diff line number Diff line
@@ -159,6 +159,13 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 
		}

	}



	/* TODO: Add queue reset mask when FW fully supports it */

	adev->jpeg.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);

	if (r)

		return r;



	return 0;

}
@@ -178,6 +185,7 @@ static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	amdgpu_jpeg_sysfs_reset_mask_fini(adev);

	r = amdgpu_jpeg_sw_fini(adev);



	return r;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

+8 −0
Original line number Diff line number Diff line
@@ -153,6 +153,13 @@ static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);

	}



	/* TODO: Add queue reset mask when FW fully supports it */

	adev->jpeg.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);

	if (r)

		return r;



	return 0;

}
@@ -172,6 +179,7 @@ static int jpeg_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	amdgpu_jpeg_sysfs_reset_mask_fini(adev);

	r = amdgpu_jpeg_sw_fini(adev);



	return r;