Commit 96f18263 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Lucas De Marchi
Browse files

drm/xe/xelp: Add Wa_1604555607 



According to the i915 code base and as confirmed in the workaround
database, apart from setting the GS timer, all XeLP platforms should also
set the TDS timer.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@igalia.com>
References: 2b5298b0 ("drm/i915/gen12: Add recommended hardware tuning value")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250227101304.46660-4-tvrtko.ursulin@igalia.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent d9b5d83c

drivers/gpu/drm/xe/xe_wa.c

+7 −0
Original line number Diff line number Diff line
@@ -636,6 +636,13 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
						FF_MODE2_GS_TIMER_MASK,

						FF_MODE2_GS_TIMER_224))

	},

	{ XE_RTP_NAME("1604555607"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),

	  /* read verification is ignored due to 1608008084. */

	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,

						FF_MODE2_TDS_TIMER_MASK,

						FF_MODE2_TDS_TIMER_128))

	},

	{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,