Commit 96f3b978 authored by Dmitry Rokosov's avatar Dmitry Rokosov Committed by Jerome Brunet
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dt-bindings: clock: meson: a1: pll: introduce new syspll bindings 



The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.

The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.

Signed-off-by: default avatarDmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent fc1c7f94

Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

+7 −2
Original line number Diff line number Diff line
@@ -26,11 +26,15 @@ properties: 
    items:

      - description: input fixpll_in

      - description: input hifipll_in

      - description: input syspll_in

    minItems: 2 # syspll_in is optional



  clock-names:

    items:

      - const: fixpll_in

      - const: hifipll_in

      - const: syspll_in

    minItems: 2 # syspll_in is optional



required:

  - compatible
@@ -53,7 +57,8 @@ examples: 
            reg = <0 0x7c80 0 0x18c>;

            #clock-cells = <1>;

            clocks = <&clkc_periphs CLKID_FIXPLL_IN>,

                     <&clkc_periphs CLKID_HIFIPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in";

                     <&clkc_periphs CLKID_HIFIPLL_IN>,

                     <&clkc_periphs CLKID_SYSPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in", "syspll_in";

        };

    };

include/dt-bindings/clock/amlogic,a1-pll-clkc.h

+1 −0
Original line number Diff line number Diff line
@@ -21,5 +21,6 @@ 
#define CLKID_FCLK_DIV5		8

#define CLKID_FCLK_DIV7		9

#define CLKID_HIFI_PLL		10

#define CLKID_SYS_PLL		11



#endif /* __A1_PLL_CLKC_H */