ASoC: Intel: Remove unused code (970d299b) · Commits · git / linux-net

sound/soc/intel/Kconfig

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		@@ -15,9 +15,6 @@ config SND_SOC_INTEL_SST_TOPLEVEL

		if SND_SOC_INTEL_SST_TOPLEVEL

		config SND_SOC_INTEL_SST
		tristate

		config SND_SOC_INTEL_CATPT
		tristate "Haswell and Broadwell"
		depends on ACPI \|\| COMPILE_TEST

sound/soc/intel/common/Makefile

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		# SPDX-License-Identifier: GPL-2.0-only
		snd-soc-sst-dsp-y := sst-dsp.o
		snd-soc-sst-ipc-y := sst-ipc.o
		snd-soc-acpi-intel-match-y := soc-acpi-intel-byt-match.o soc-acpi-intel-cht-match.o \
		soc-acpi-intel-hsw-bdw-match.o \
		soc-acpi-intel-skl-match.o soc-acpi-intel-kbl-match.o \
		@@ -18,5 +16,4 @@ snd-soc-acpi-intel-match-y := soc-acpi-intel-byt-match.o soc-acpi-intel-cht-matc

		snd-soc-acpi-intel-match-y += soc-acpi-intel-ssp-common.o

		obj-$(CONFIG_SND_SOC_INTEL_SST) += snd-soc-sst-dsp.o snd-soc-sst-ipc.o
		obj-$(CONFIG_SND_SOC_ACPI_INTEL_MATCH) += snd-soc-acpi-intel-match.o

sound/soc/intel/common/sst-dsp-priv.h

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		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Intel Smart Sound Technology
		*
		* Copyright (C) 2013, Intel Corporation
		*/

		#ifndef __SOUND_SOC_SST_DSP_PRIV_H
		#define __SOUND_SOC_SST_DSP_PRIV_H

		#include <linux/kernel.h>
		#include <linux/types.h>
		#include <linux/interrupt.h>
		#include <linux/firmware.h>

		#include "../skylake/skl-sst-dsp.h"

		/*
		* DSP Operations exported by platform Audio DSP driver.
		*/
		struct sst_ops {
		/* Shim IO */
		void (write)(void __iomem addr, u32 offset, u32 value);
		u32 (read)(void __iomem addr, u32 offset);

		/* IRQ handlers */
		irqreturn_t (irq_handler)(int irq, void context);

		/* SST init and free */
		int (init)(struct sst_dsp sst);
		void (free)(struct sst_dsp sst);
		};

		/*
		* Audio DSP memory offsets and addresses.
		*/
		struct sst_addr {
		u32 sram0_base;
		u32 sram1_base;
		u32 w0_stat_sz;
		u32 w0_up_sz;
		void __iomem *lpe;
		void __iomem *shim;
		};

		/*
		* Audio DSP Mailbox configuration.
		*/
		struct sst_mailbox {
		void __iomem *in_base;
		void __iomem *out_base;
		size_t in_size;
		size_t out_size;
		};

		/*
		* Generic SST Shim Interface.
		*/
		struct sst_dsp {

		/* Shared for all platforms */

		/* runtime */
		struct sst_dsp_device *sst_dev;
		spinlock_t spinlock; /* IPC locking */
		struct mutex mutex; /* DSP FW lock */
		struct device *dev;
		void *thread_context;
		int irq;
		u32 id;

		/* operations */
		struct sst_ops *ops;

		/* debug FS */
		struct dentry *debugfs_root;

		/* base addresses */
		struct sst_addr addr;

		/* mailbox */
		struct sst_mailbox mailbox;

		/* SST FW files loaded and their modules */
		struct list_head module_list;

		/* SKL data */

		const char *fw_name;

		/* To allocate CL dma buffers */
		struct skl_dsp_loader_ops dsp_ops;
		struct skl_dsp_fw_ops fw_ops;
		int sst_state;
		struct skl_cl_dev cl_dev;
		u32 intr_status;
		const struct firmware *fw;
		struct snd_dma_buffer dmab;
		};

		#endif

sound/soc/intel/common/sst-dsp.c

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Intel Smart Sound Technology (SST) DSP Core Driver
		*
		* Copyright (C) 2013, Intel Corporation
		*/

		#include <linux/slab.h>
		#include <linux/export.h>
		#include <linux/interrupt.h>
		#include <linux/module.h>
		#include <linux/platform_device.h>
		#include <linux/io-64-nonatomic-lo-hi.h>
		#include <linux/delay.h>

		#include "sst-dsp.h"
		#include "sst-dsp-priv.h"

		#define CREATE_TRACE_POINTS
		#include <trace/events/intel-sst.h>

		/* Internal generic low-level SST IO functions - can be overidden */
		void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
		{
		writel(value, addr + offset);
		}
		EXPORT_SYMBOL_GPL(sst_shim32_write);

		u32 sst_shim32_read(void __iomem *addr, u32 offset)
		{
		return readl(addr + offset);
		}
		EXPORT_SYMBOL_GPL(sst_shim32_read);

		void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
		{
		writeq(value, addr + offset);
		}
		EXPORT_SYMBOL_GPL(sst_shim32_write64);

		u64 sst_shim32_read64(void __iomem *addr, u32 offset)
		{
		return readq(addr + offset);
		}
		EXPORT_SYMBOL_GPL(sst_shim32_read64);

		/* Public API */
		void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
		{
		unsigned long flags;

		spin_lock_irqsave(&sst->spinlock, flags);
		sst->ops->write(sst->addr.shim, offset, value);
		spin_unlock_irqrestore(&sst->spinlock, flags);
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_write);

		u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
		{
		unsigned long flags;
		u32 val;

		spin_lock_irqsave(&sst->spinlock, flags);
		val = sst->ops->read(sst->addr.shim, offset);
		spin_unlock_irqrestore(&sst->spinlock, flags);

		return val;
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_read);

		void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
		{
		sst->ops->write(sst->addr.shim, offset, value);
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);

		u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
		{
		return sst->ops->read(sst->addr.shim, offset);
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);

		int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value)
		{
		bool change;
		unsigned int old, new;
		u32 ret;

		ret = sst_dsp_shim_read_unlocked(sst, offset);

		old = ret;
		new = (old & (~mask)) \| (value & mask);

		change = (old != new);
		if (change)
		sst_dsp_shim_write_unlocked(sst, offset, new);

		return change;
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);

		/* This is for registers bits with attribute RWC */
		void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value)
		{
		unsigned int old, new;
		u32 ret;

		ret = sst_dsp_shim_read_unlocked(sst, offset);

		old = ret;
		new = (old & (~mask)) \| (value & mask);

		sst_dsp_shim_write_unlocked(sst, offset, new);
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);

		int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value)
		{
		unsigned long flags;
		bool change;

		spin_lock_irqsave(&sst->spinlock, flags);
		change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
		spin_unlock_irqrestore(&sst->spinlock, flags);
		return change;
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);

		/* This is for registers bits with attribute RWC */
		void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value)
		{
		unsigned long flags;

		spin_lock_irqsave(&sst->spinlock, flags);
		sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
		spin_unlock_irqrestore(&sst->spinlock, flags);
		}
		EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);

		int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
		u32 target, u32 time, char *operation)
		{
		u32 reg;
		unsigned long timeout;
		int k = 0, s = 500;

		/*
		* split the loop into sleeps of varying resolution. more accurately,
		* the range of wakeups are:
		* Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
		* Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
		* (usleep_range (500, 1000) and usleep_range(5000, 10000) are
		* both possible in this phase depending on whether k > 10 or not).
		* Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
		*/

		timeout = jiffies + msecs_to_jiffies(time);
		while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
		&& time_before(jiffies, timeout)) {
		k++;
		if (k > 10)
		s = 5000;

		usleep_range(s, 2*s);
		}

		if ((reg & mask) == target) {
		dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
		reg, operation);

		return 0;
		}

		dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
		reg, operation);
		return -ETIME;
		}
		EXPORT_SYMBOL_GPL(sst_dsp_register_poll);

		int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
		u32 outbox_offset, size_t outbox_size)
		{
		sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
		sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
		sst->mailbox.in_size = inbox_size;
		sst->mailbox.out_size = outbox_size;
		return 0;
		}
		EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);

		void sst_dsp_outbox_write(struct sst_dsp sst, void message, size_t bytes)
		{
		u32 i;

		trace_sst_ipc_outbox_write(bytes);

		memcpy_toio(sst->mailbox.out_base, message, bytes);

		for (i = 0; i < bytes; i += 4)
		trace_sst_ipc_outbox_wdata(i, (u32 )(message + i));
		}
		EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);

		void sst_dsp_outbox_read(struct sst_dsp sst, void message, size_t bytes)
		{
		u32 i;

		trace_sst_ipc_outbox_read(bytes);

		memcpy_fromio(message, sst->mailbox.out_base, bytes);

		for (i = 0; i < bytes; i += 4)
		trace_sst_ipc_outbox_rdata(i, (u32 )(message + i));
		}
		EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);

		void sst_dsp_inbox_write(struct sst_dsp sst, void message, size_t bytes)
		{
		u32 i;

		trace_sst_ipc_inbox_write(bytes);

		memcpy_toio(sst->mailbox.in_base, message, bytes);

		for (i = 0; i < bytes; i += 4)
		trace_sst_ipc_inbox_wdata(i, (u32 )(message + i));
		}
		EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);

		void sst_dsp_inbox_read(struct sst_dsp sst, void message, size_t bytes)
		{
		u32 i;

		trace_sst_ipc_inbox_read(bytes);

		memcpy_fromio(message, sst->mailbox.in_base, bytes);

		for (i = 0; i < bytes; i += 4)
		trace_sst_ipc_inbox_rdata(i, (u32 )(message + i));
		}
		EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);

		/* Module information */
		MODULE_AUTHOR("Liam Girdwood");
		MODULE_DESCRIPTION("Intel SST Core");
		MODULE_LICENSE("GPL v2");

sound/soc/intel/common/sst-dsp.h

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		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Intel Smart Sound Technology (SST) Core
		*
		* Copyright (C) 2013, Intel Corporation
		*/

		#ifndef __SOUND_SOC_SST_DSP_H
		#define __SOUND_SOC_SST_DSP_H

		#include <linux/kernel.h>
		#include <linux/types.h>
		#include <linux/interrupt.h>

		struct sst_dsp;

		/*
		* SST Device.
		*
		* This structure is populated by the SST core driver.
		*/
		struct sst_dsp_device {
		/* Mandatory fields */
		struct sst_ops *ops;
		irqreturn_t (thread)(int irq, void context);
		void *thread_context;
		};

		/* SHIM Read / Write */
		void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
		u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
		int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value);
		void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value);

		/* SHIM Read / Write Unlocked for callers already holding sst lock */
		void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
		u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
		int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value);
		void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
		u32 mask, u32 value);

		/* Internal generic low-level SST IO functions - can be overidden */
		void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
		u32 sst_shim32_read(void __iomem *addr, u32 offset);
		void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
		u64 sst_shim32_read64(void __iomem *addr, u32 offset);

		/* Mailbox management */
		int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset,
		size_t inbox_size, u32 outbox_offset, size_t outbox_size);
		void sst_dsp_inbox_write(struct sst_dsp sst, void message, size_t bytes);
		void sst_dsp_inbox_read(struct sst_dsp sst, void message, size_t bytes);
		void sst_dsp_outbox_write(struct sst_dsp sst, void message, size_t bytes);
		void sst_dsp_outbox_read(struct sst_dsp sst, void message, size_t bytes);
		int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
		u32 target, u32 time, char *operation);

		#endif