Commit 9724b849 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: restore immediate_disable_crtc for w/a 



[why]
immediate_disable_crtc does not reset ODM.  if switching to disable_crtc
which will disable ODM as well.  i.e. need to restore ODM mem cfg at
reenable it at end of w/a.

Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarXi (Alex) Liu <xi.liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 739d0f3e

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -149,8 +149,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state * 
			!pipe->stream->link_enc) && !stream_changed_otg_dig_on) {

			/* This w/a should not trigger when we have a dig active */

			if (disable) {

				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->disable_crtc)

					pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);



				reset_sync_context_for_pipe(dc, context, i);

			} else {

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

+6 −2
Original line number Diff line number Diff line
@@ -149,7 +149,9 @@ static bool optc31_disable_crtc(struct timing_generator *optc) 


	return true;

}



/*

 * Immediate_Disable_Crtc - this is to temp disable Timing generator without reset ODM.

 */

bool optc31_immediate_disable_crtc(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -162,10 +164,12 @@ bool optc31_immediate_disable_crtc(struct timing_generator *optc) 
			VTG0_ENABLE, 0);



	/* CRTC disabled, so disable  clock. */

	if (optc->ctx->dce_environment != DCE_ENV_DIAG)

		REG_WAIT(OTG_CLOCK_CONTROL,

			OTG_BUSY, 0,

			1, 100000);





	/* clear the false state */

	optc1_clear_optc_underflow(optc);