Commit 97300913 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Joerg Roedel
Browse files

iommu/vt-d: Remove dmar_readl() and dmar_readq() 



dmar_readl() and dmar_readq() do nothing other than expand to the generic
readl() and readq(), and the dmar_read*() wrappers are used inconsistently.

Remove the dmar_read*() wrappers and use readl() and readq() directly.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarSamiullah Khawaja <skhawaja@google.com>
Link: https://lore.kernel.org/r/20260217214438.3395039-2-bhelgaas@google.com


Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent c9587216

drivers/iommu/intel/debugfs.c

+9 −9
Original line number Diff line number Diff line
@@ -133,13 +133,13 @@ static int iommu_regset_show(struct seq_file *m, void *unused) 
		 */

		raw_spin_lock_irqsave(&iommu->register_lock, flag);

		for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {

			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);

			value = readl(iommu->reg + iommu_regs_32[i].offset);

			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",

				   iommu_regs_32[i].regs, iommu_regs_32[i].offset,

				   value);

		}

		for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {

			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);

			value = readq(iommu->reg + iommu_regs_64[i].offset);

			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",

				   iommu_regs_64[i].regs, iommu_regs_64[i].offset,

				   value);
@@ -247,7 +247,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) 
		tbl_wlk.ctx_entry = context;

		m->private = &tbl_wlk;



		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {

		if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {

			pasid_dir_ptr = context->lo & VTD_PAGE_MASK;

			pasid_dir_size = get_pasid_dir_size(context);

			pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
@@ -285,7 +285,7 @@ static int dmar_translation_struct_show(struct seq_file *m, void *unused) 


	rcu_read_lock();

	for_each_active_iommu(iommu, drhd) {

		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);

		sts = readl(iommu->reg + DMAR_GSTS_REG);

		if (!(sts & DMA_GSTS_TES)) {

			seq_printf(m, "DMA Remapping is not enabled on %s\n",

				   iommu->name);
@@ -364,13 +364,13 @@ static int domain_translation_struct_show(struct seq_file *m, 
		if (seg != iommu->segment)

			continue;



		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);

		sts = readl(iommu->reg + DMAR_GSTS_REG);

		if (!(sts & DMA_GSTS_TES)) {

			seq_printf(m, "DMA Remapping is not enabled on %s\n",

				   iommu->name);

			continue;

		}

		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)

		if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)

			scalable = true;

		else

			scalable = false;
@@ -538,8 +538,8 @@ static int invalidation_queue_show(struct seq_file *m, void *unused) 
		raw_spin_lock_irqsave(&qi->q_lock, flags);

		seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",

			   (u64)virt_to_phys(qi->desc),

			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,

			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);

			   readq(iommu->reg + DMAR_IQH_REG) >> shift,

			   readq(iommu->reg + DMAR_IQT_REG) >> shift);

		invalidation_queue_entry_show(m, iommu);

		raw_spin_unlock_irqrestore(&qi->q_lock, flags);

		seq_putc(m, '\n');
@@ -620,7 +620,7 @@ static int ir_translation_struct_show(struct seq_file *m, void *unused) 
		seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",

			   iommu->name);



		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);

		sts = readl(iommu->reg + DMAR_GSTS_REG);

		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {

			irta = virt_to_phys(iommu->ir_table->base);

			seq_printf(m, " IR table address:%llx\n", irta);

drivers/iommu/intel/dmar.c

+11 −11
Original line number Diff line number Diff line
@@ -899,8 +899,8 @@ dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) 
		return -EINVAL;

	}



	cap = dmar_readq(addr + DMAR_CAP_REG);

	ecap = dmar_readq(addr + DMAR_ECAP_REG);

	cap = readq(addr + DMAR_CAP_REG);

	ecap = readq(addr + DMAR_ECAP_REG);



	if (arg)

		iounmap(addr);
@@ -982,8 +982,8 @@ static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd) 
		goto release;

	}



	iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);

	iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);

	iommu->cap = readq(iommu->reg + DMAR_CAP_REG);

	iommu->ecap = readq(iommu->reg + DMAR_ECAP_REG);



	if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {

		err = -EINVAL;
@@ -1017,7 +1017,7 @@ static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd) 
		int i;



		for (i = 0; i < DMA_MAX_NUM_ECMDCAP; i++) {

			iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG +

			iommu->ecmdcap[i] = readq(iommu->reg + DMAR_ECCAP_REG +

						  i * DMA_ECMD_REG_STEP);

		}

	}
@@ -1239,8 +1239,8 @@ static const char *qi_type_string(u8 type) 


static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)

{

	unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);

	u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);

	unsigned int head = readl(iommu->reg + DMAR_IQH_REG);

	u64 iqe_err = readq(iommu->reg + DMAR_IQER_REG);

	struct qi_desc *desc = iommu->qi->desc + head;



	if (fault & DMA_FSTS_IQE)
@@ -1322,7 +1322,7 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) 
		 * SID field is valid only when the ITE field is Set in FSTS_REG

		 * see Intel VT-d spec r4.1, section 11.4.9.9

		 */

		iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);

		iqe_err = readq(iommu->reg + DMAR_IQER_REG);

		ite_sid = DMAR_IQER_REG_ITESID(iqe_err);



		writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
@@ -1981,7 +1981,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id) 
			source_id = dma_frcd_source_id(data);



			pasid_present = dma_frcd_pasid_present(data);

			guest_addr = dmar_readq(iommu->reg + reg +

			guest_addr = readq(iommu->reg + reg +

					   fault_index * PRIMARY_FAULT_REG_LEN);

			guest_addr = dma_frcd_page_addr(guest_addr);

		}

drivers/iommu/intel/iommu.c

+5 −5
Original line number Diff line number Diff line
@@ -769,7 +769,7 @@ static void __iommu_flush_context(struct intel_iommu *iommu, 


	/* Make sure hardware complete it */

	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,

		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

		readq, (!(val & DMA_CCMD_ICC)), val);



	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);

}
@@ -811,7 +811,7 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, 


	/* Make sure hardware complete it */

	IOMMU_WAIT_OP(iommu, tlb_offset + 8,

		dmar_readq, (!(val & DMA_TLB_IVT)), val);

		readq, (!(val & DMA_TLB_IVT)), val);



	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
@@ -1533,7 +1533,7 @@ static int copy_translation_tables(struct intel_iommu *iommu) 
	int bus, ret;

	bool new_ext, ext;



	rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);

	rtaddr_reg = readq(iommu->reg + DMAR_RTADDR_REG);

	ext        = !!(rtaddr_reg & DMA_RTADDR_SMT);

	new_ext    = !!sm_supported(iommu);
@@ -4188,7 +4188,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob) 


	raw_spin_lock_irqsave(&iommu->register_lock, flags);



	res = dmar_readq(iommu->reg + DMAR_ECRSP_REG);

	res = readq(iommu->reg + DMAR_ECRSP_REG);

	if (res & DMA_ECMD_ECRSP_IP) {

		ret = -EBUSY;

		goto err;
@@ -4204,7 +4204,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob) 
	dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob);

	dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT));



	IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq,

	IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq,

		      !(res & DMA_ECMD_ECRSP_IP), res);



	if (res & DMA_ECMD_ECRSP_IP) {

drivers/iommu/intel/iommu.h

+0 −2
Original line number Diff line number Diff line
@@ -148,9 +148,7 @@ 


#define OFFSET_STRIDE		(9)



#define dmar_readq(a) readq(a)

#define dmar_writeq(a,v) writeq(v,a)

#define dmar_readl(a) readl(a)

#define dmar_writel(a, v) writel(v, a)



#define DMAR_VER_MAJOR(v)		(((v) & 0xf0) >> 4)

drivers/iommu/intel/irq_remapping.c

+1 −1
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ static int iommu_load_old_irte(struct intel_iommu *iommu) 
	u64 irta;



	/* Check whether the old ir-table has the same size as ours */

	irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);

	irta = readq(iommu->reg + DMAR_IRTA_REG);

	if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)

	     != INTR_REMAP_TABLE_REG_SIZE)

		return -EINVAL;