Commit 97bb5e69 authored by Haridhar Kalvala's avatar Haridhar Kalvala Committed by Matt Roper
Browse files

drm/i915: Add Wa_14019877138 



Enable Force Dispatch Ends Collection for DG2.

BSpec: 46001

Signed-off-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231213064612.480032-1-haridhar.kalvala@intel.com
parent afa5cf31

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -469,6 +469,9 @@ 
#define XEHP_PSS_MODE2				MCR_REG(0x703c)

#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)



#define XEHP_PSS_CHICKEN			MCR_REG(0x7044)

#define   FD_END_COLLECT			REG_BIT(5)



#define GEN7_SC_INSTDONE			_MMIO(0x7100)

#define GEN12_SC_INSTDONE_EXTRA			_MMIO(0x7104)

#define GEN12_SC_INSTDONE_EXTRA2		_MMIO(0x7108)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -777,6 +777,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 


	/* Wa_18019271663:dg2 */

	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);



	/* Wa_14019877138:dg2 */

	wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);

}



static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,