Commit 97d61bf9 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

rtw89: pci: add V1 of PCI channel address 



8852CE use V1 address, and flow is totally shared with 8852AE.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220307060457.56789-4-pkshih@realtek.com
parent 4a9e48ac

drivers/net/wireless/realtek/rtw89/pci.c

+106 −76
Original line number Diff line number Diff line
@@ -697,71 +697,110 @@ static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) 
	return irqret;

}



#define case_TXCHADDRS(txch) \

	case RTW89_TXCH_##txch: \

		*addr_num = R_AX_##txch##_TXBD_NUM; \

		*addr_idx = R_AX_##txch##_TXBD_IDX; \

		*addr_bdram = R_AX_##txch##_BDRAM_CTRL; \

		*addr_desa_l = R_AX_##txch##_TXBD_DESA_L; \

		*addr_desa_h = R_AX_##txch##_TXBD_DESA_H; \

		break



static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch,

				    u32 *addr_num,

				    u32 *addr_idx,

				    u32 *addr_bdram,

				    u32 *addr_desa_l,

				    u32 *addr_desa_h)

{

	switch (txch) {

	case_TXCHADDRS(ACH0);

	case_TXCHADDRS(ACH1);

	case_TXCHADDRS(ACH2);

	case_TXCHADDRS(ACH3);

	case_TXCHADDRS(ACH4);

	case_TXCHADDRS(ACH5);

	case_TXCHADDRS(ACH6);

	case_TXCHADDRS(ACH7);

	case_TXCHADDRS(CH8);

	case_TXCHADDRS(CH9);

	case_TXCHADDRS(CH10);

	case_TXCHADDRS(CH11);

	case_TXCHADDRS(CH12);

	default:

#define DEF_TXCHADDRS_TYPE1(info, txch, v...) \

	[RTW89_TXCH_##txch] = { \

		.num = R_AX_##txch##_TXBD_NUM ##v, \

		.idx = R_AX_##txch##_TXBD_IDX ##v, \

		.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \

		.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \

		.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \

	}



#define DEF_TXCHADDRS(info, txch, v...) \

	[RTW89_TXCH_##txch] = { \

		.num = R_AX_##txch##_TXBD_NUM, \

		.idx = R_AX_##txch##_TXBD_IDX, \

		.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \

		.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \

		.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \

	}



#define DEF_RXCHADDRS(info, rxch, v...) \

	[RTW89_RXCH_##rxch] = { \

		.num = R_AX_##rxch##_RXBD_NUM ##v, \

		.idx = R_AX_##rxch##_RXBD_IDX ##v, \

		.desa_l = R_AX_##rxch##_RXBD_DESA_L ##v, \

		.desa_h = R_AX_##rxch##_RXBD_DESA_H ##v, \

	}



const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set = {

	.tx = {

		DEF_TXCHADDRS(info, ACH0),

		DEF_TXCHADDRS(info, ACH1),

		DEF_TXCHADDRS(info, ACH2),

		DEF_TXCHADDRS(info, ACH3),

		DEF_TXCHADDRS(info, ACH4),

		DEF_TXCHADDRS(info, ACH5),

		DEF_TXCHADDRS(info, ACH6),

		DEF_TXCHADDRS(info, ACH7),

		DEF_TXCHADDRS(info, CH8),

		DEF_TXCHADDRS(info, CH9),

		DEF_TXCHADDRS_TYPE1(info, CH10),

		DEF_TXCHADDRS_TYPE1(info, CH11),

		DEF_TXCHADDRS(info, CH12),

	},

	.rx = {

		DEF_RXCHADDRS(info, RXQ),

		DEF_RXCHADDRS(info, RPQ),

	},

};

EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set);



const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1 = {

	.tx = {

		DEF_TXCHADDRS(info, ACH0, _V1),

		DEF_TXCHADDRS(info, ACH1, _V1),

		DEF_TXCHADDRS(info, ACH2, _V1),

		DEF_TXCHADDRS(info, ACH3, _V1),

		DEF_TXCHADDRS(info, ACH4, _V1),

		DEF_TXCHADDRS(info, ACH5, _V1),

		DEF_TXCHADDRS(info, ACH6, _V1),

		DEF_TXCHADDRS(info, ACH7, _V1),

		DEF_TXCHADDRS(info, CH8, _V1),

		DEF_TXCHADDRS(info, CH9, _V1),

		DEF_TXCHADDRS_TYPE1(info, CH10, _V1),

		DEF_TXCHADDRS_TYPE1(info, CH11, _V1),

		DEF_TXCHADDRS(info, CH12, _V1),

	},

	.rx = {

		DEF_RXCHADDRS(info, RXQ, _V1),

		DEF_RXCHADDRS(info, RPQ, _V1),

	},

};

EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_v1);



#undef DEF_TXCHADDRS_TYPE1

#undef DEF_TXCHADDRS

#undef DEF_RXCHADDRS



static int rtw89_pci_get_txch_addrs(struct rtw89_dev *rtwdev,

				    enum rtw89_tx_channel txch,

				    const struct rtw89_pci_ch_dma_addr **addr)

{

	const struct rtw89_pci_info *info = rtwdev->pci_info;



	if (txch >= RTW89_TXCH_NUM)

		return -EINVAL;

	}



	*addr = &info->dma_addr_set->tx[txch];



	return 0;

}



#undef case_TXCHADDRS



#define case_RXCHADDRS(rxch) \

	case RTW89_RXCH_##rxch: \

		*addr_num = R_AX_##rxch##_RXBD_NUM; \

		*addr_idx = R_AX_##rxch##_RXBD_IDX; \

		*addr_desa_l = R_AX_##rxch##_RXBD_DESA_L; \

		*addr_desa_h = R_AX_##rxch##_RXBD_DESA_H; \

		break



static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch,

				    u32 *addr_num,

				    u32 *addr_idx,

				    u32 *addr_desa_l,

				    u32 *addr_desa_h)

static int rtw89_pci_get_rxch_addrs(struct rtw89_dev *rtwdev,

				    enum rtw89_rx_channel rxch,

				    const struct rtw89_pci_ch_dma_addr **addr)

{

	switch (rxch) {

	case_RXCHADDRS(RXQ);

	case_RXCHADDRS(RPQ);

	default:

	const struct rtw89_pci_info *info = rtwdev->pci_info;



	if (rxch >= RTW89_RXCH_NUM)

		return -EINVAL;

	}



	*addr = &info->dma_addr_set->rx[rxch];



	return 0;

}



#undef case_RXCHADDRS



static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring)

{

	struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring;
@@ -2188,14 +2227,10 @@ static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 
				   u32 desc_size, u32 len,

				   enum rtw89_tx_channel txch)

{

	const struct rtw89_pci_ch_dma_addr *txch_addr;

	int ring_sz = desc_size * len;

	u8 *head;

	dma_addr_t dma;

	u32 addr_num;

	u32 addr_idx;

	u32 addr_bdram;

	u32 addr_desa_l;

	u32 addr_desa_h;

	int ret;



	ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch);
@@ -2204,8 +2239,7 @@ static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 
		goto err;

	}



	ret = rtw89_pci_get_txch_addrs(txch, &addr_num, &addr_idx, &addr_bdram,

				       &addr_desa_l, &addr_desa_h);

	ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr);

	if (ret) {

		rtw89_err(rtwdev, "failed to get address of txch %d", txch);

		goto err_free_wd_ring;
@@ -2222,11 +2256,11 @@ static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 
	tx_ring->bd_ring.dma = dma;

	tx_ring->bd_ring.len = len;

	tx_ring->bd_ring.desc_size = desc_size;

	tx_ring->bd_ring.addr_num = addr_num;

	tx_ring->bd_ring.addr_idx = addr_idx;

	tx_ring->bd_ring.addr_bdram = addr_bdram;

	tx_ring->bd_ring.addr_desa_l = addr_desa_l;

	tx_ring->bd_ring.addr_desa_h = addr_desa_h;

	tx_ring->bd_ring.addr_num = txch_addr->num;

	tx_ring->bd_ring.addr_idx = txch_addr->idx;

	tx_ring->bd_ring.addr_bdram = txch_addr->bdram;

	tx_ring->bd_ring.addr_desa_l = txch_addr->desa_l;

	tx_ring->bd_ring.addr_desa_h = txch_addr->desa_h;

	tx_ring->bd_ring.wp = 0;

	tx_ring->bd_ring.rp = 0;

	tx_ring->txch = txch;
@@ -2278,20 +2312,16 @@ static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 
				   struct rtw89_pci_rx_ring *rx_ring,

				   u32 desc_size, u32 len, u32 rxch)

{

	const struct rtw89_pci_ch_dma_addr *rxch_addr;

	struct sk_buff *skb;

	u8 *head;

	dma_addr_t dma;

	u32 addr_num;

	u32 addr_idx;

	u32 addr_desa_l;

	u32 addr_desa_h;

	int ring_sz = desc_size * len;

	int buf_sz = RTW89_PCI_RX_BUF_SIZE;

	int i, allocated;

	int ret;



	ret = rtw89_pci_get_rxch_addrs(rxch, &addr_num, &addr_idx,

				       &addr_desa_l, &addr_desa_h);

	ret = rtw89_pci_get_rxch_addrs(rtwdev, rxch, &rxch_addr);

	if (ret) {

		rtw89_err(rtwdev, "failed to get address of rxch %d", rxch);

		return ret;
@@ -2307,10 +2337,10 @@ static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 
	rx_ring->bd_ring.dma = dma;

	rx_ring->bd_ring.len = len;

	rx_ring->bd_ring.desc_size = desc_size;

	rx_ring->bd_ring.addr_num = addr_num;

	rx_ring->bd_ring.addr_idx = addr_idx;

	rx_ring->bd_ring.addr_desa_l = addr_desa_l;

	rx_ring->bd_ring.addr_desa_h = addr_desa_h;

	rx_ring->bd_ring.addr_num = rxch_addr->num;

	rx_ring->bd_ring.addr_idx = rxch_addr->idx;

	rx_ring->bd_ring.addr_desa_l = rxch_addr->desa_l;

	rx_ring->bd_ring.addr_desa_h = rxch_addr->desa_h;

	rx_ring->bd_ring.wp = 0;

	rx_ring->bd_ring.rp = 0;

	rx_ring->buf_sz = buf_sz;

drivers/net/wireless/realtek/rtw89/pci.h

+67 −0
Original line number Diff line number Diff line
@@ -130,6 +130,10 @@ 
#define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */

#define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */

#define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */

#define R_AX_CH10_TXBD_IDX_V1	0x11D0

#define R_AX_CH11_TXBD_IDX_V1	0x11D4

#define R_AX_RXQ_RXBD_IDX_V1	0x1218

#define R_AX_RPQ_RXBD_IDX_V1	0x121C

#define TXBD_HW_IDX_MASK	GENMASK(27, 16)

#define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
@@ -163,6 +167,36 @@ 
#define R_AX_RXQ_RXBD_DESA_H	0x1104

#define R_AX_RPQ_RXBD_DESA_L	0x1108

#define R_AX_RPQ_RXBD_DESA_H	0x110C

#define R_AX_RXQ_RXBD_DESA_L_V1 0x1220

#define R_AX_RXQ_RXBD_DESA_H_V1 0x1224

#define R_AX_RPQ_RXBD_DESA_L_V1 0x1228

#define R_AX_RPQ_RXBD_DESA_H_V1 0x122C

#define R_AX_ACH0_TXBD_DESA_L_V1 0x1230

#define R_AX_ACH0_TXBD_DESA_H_V1 0x1234

#define R_AX_ACH1_TXBD_DESA_L_V1 0x1238

#define R_AX_ACH1_TXBD_DESA_H_V1 0x123C

#define R_AX_ACH2_TXBD_DESA_L_V1 0x1240

#define R_AX_ACH2_TXBD_DESA_H_V1 0x1244

#define R_AX_ACH3_TXBD_DESA_L_V1 0x1248

#define R_AX_ACH3_TXBD_DESA_H_V1 0x124C

#define R_AX_ACH4_TXBD_DESA_L_V1 0x1250

#define R_AX_ACH4_TXBD_DESA_H_V1 0x1254

#define R_AX_ACH5_TXBD_DESA_L_V1 0x1258

#define R_AX_ACH5_TXBD_DESA_H_V1 0x125C

#define R_AX_ACH6_TXBD_DESA_L_V1 0x1260

#define R_AX_ACH6_TXBD_DESA_H_V1 0x1264

#define R_AX_ACH7_TXBD_DESA_L_V1 0x1268

#define R_AX_ACH7_TXBD_DESA_H_V1 0x126C

#define R_AX_CH8_TXBD_DESA_L_V1 0x1270

#define R_AX_CH8_TXBD_DESA_H_V1 0x1274

#define R_AX_CH9_TXBD_DESA_L_V1 0x1278

#define R_AX_CH9_TXBD_DESA_H_V1 0x127C

#define R_AX_CH12_TXBD_DESA_L_V1 0x1280

#define R_AX_CH12_TXBD_DESA_H_V1 0x1284

#define R_AX_CH10_TXBD_DESA_L_V1 0x1458

#define R_AX_CH10_TXBD_DESA_H_V1 0x145C

#define R_AX_CH11_TXBD_DESA_L_V1 0x1460

#define R_AX_CH11_TXBD_DESA_H_V1 0x1464

#define B_AX_DESC_NUM_MSK		GENMASK(11, 0)



#define R_AX_RXQ_RXBD_NUM	0x1020
@@ -180,6 +214,10 @@ 
#define R_AX_CH10_TXBD_NUM	0x1338

#define R_AX_CH11_TXBD_NUM	0x133A

#define R_AX_CH12_TXBD_NUM	0x1038

#define R_AX_RXQ_RXBD_NUM_V1	0x1210

#define R_AX_RPQ_RXBD_NUM_V1	0x1212

#define R_AX_CH10_TXBD_NUM_V1	0x1438

#define R_AX_CH11_TXBD_NUM_V1	0x143A



#define R_AX_ACH0_BDRAM_CTRL	0x1200

#define R_AX_ACH1_BDRAM_CTRL	0x1204
@@ -194,6 +232,19 @@ 
#define R_AX_CH10_BDRAM_CTRL	0x1320

#define R_AX_CH11_BDRAM_CTRL	0x1324

#define R_AX_CH12_BDRAM_CTRL	0x1228

#define R_AX_ACH0_BDRAM_CTRL_V1 0x1300

#define R_AX_ACH1_BDRAM_CTRL_V1 0x1304

#define R_AX_ACH2_BDRAM_CTRL_V1 0x1308

#define R_AX_ACH3_BDRAM_CTRL_V1 0x130C

#define R_AX_ACH4_BDRAM_CTRL_V1 0x1310

#define R_AX_ACH5_BDRAM_CTRL_V1 0x1314

#define R_AX_ACH6_BDRAM_CTRL_V1 0x1318

#define R_AX_ACH7_BDRAM_CTRL_V1 0x131C

#define R_AX_CH8_BDRAM_CTRL_V1 0x1320

#define R_AX_CH9_BDRAM_CTRL_V1 0x1324

#define R_AX_CH12_BDRAM_CTRL_V1 0x1328

#define R_AX_CH10_BDRAM_CTRL_V1 0x1420

#define R_AX_CH11_BDRAM_CTRL_V1 0x1424

#define BDRAM_SIDX_MASK		GENMASK(7, 0)

#define BDRAM_MAX_MASK		GENMASK(15, 8)

#define BDRAM_MIN_MASK		GENMASK(23, 16)
@@ -382,7 +433,21 @@ enum rtw89_pcie_clkdly_hw { 
	PCIE_CLKDLY_HW_200US = 0x5,

};



struct rtw89_pci_ch_dma_addr {

	u32 num;

	u32 idx;

	u32 bdram;

	u32 desa_l;

	u32 desa_h;

};



struct rtw89_pci_ch_dma_addr_set {

	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];

	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];

};



struct rtw89_pci_info {

	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;

};



struct rtw89_pci_bd_ram {
@@ -629,6 +694,8 @@ static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) 
}



extern const struct dev_pm_ops rtw89_pm_ops;

extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;

extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;



struct pci_device_id;

drivers/net/wireless/realtek/rtw89/rtw8852ae.c

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include "rtw8852a.h"



static const struct rtw89_pci_info rtw8852a_pci_info = {

	.dma_addr_set		= &rtw89_pci_ch_dma_addr_set,

};



static const struct rtw89_driver_info rtw89_8852ae_info = {

drivers/net/wireless/realtek/rtw89/rtw8852ce.c

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include "rtw8852c.h"



static const struct rtw89_pci_info rtw8852c_pci_info = {

	.dma_addr_set		= &rtw89_pci_ch_dma_addr_set_v1,

};



static const struct rtw89_driver_info rtw89_8852ce_info = {