Commit 97eccf7d authored by Yong-Xuan Wang's avatar Yong-Xuan Wang Committed by Anup Patel
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RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM 



We extend the KVM ISA extension ONE_REG interface to allow VMM tools to
detect and enable Svade and Svadu extensions for Guest/VM. Since the
henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu
extension is available for Guest/VM and the Svade extension is allowed
to disabledonly when arch_has_hw_pte_young() is true.

Signed-off-by: default avatarYong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20240726084931.28924-4-yongxuan.wang@sifive.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent b8d48167

arch/riscv/include/uapi/asm/kvm.h

+2 −0
Original line number Diff line number Diff line
@@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_ZCF,

	KVM_RISCV_ISA_EXT_ZCMOP,

	KVM_RISCV_ISA_EXT_ZAWRS,

	KVM_RISCV_ISA_EXT_SVADE,

	KVM_RISCV_ISA_EXT_SVADU,

	KVM_RISCV_ISA_EXT_MAX,

};

arch/riscv/kvm/vcpu.c

+4 −0
Original line number Diff line number Diff line
@@ -551,6 +551,10 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) 
	if (riscv_isa_extension_available(isa, ZICBOZ))

		cfg->henvcfg |= ENVCFG_CBZE;



	if (riscv_isa_extension_available(isa, SVADU) &&

	    !riscv_isa_extension_available(isa, SVADE))

		cfg->henvcfg |= ENVCFG_ADUE;



	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {

		cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;

		if (riscv_isa_extension_available(isa, SSAIA))

arch/riscv/kvm/vcpu_onereg.c

+15 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <asm/cacheflush.h>

#include <asm/cpufeature.h>

#include <asm/kvm_vcpu_vector.h>

#include <asm/pgtable.h>

#include <asm/vector.h>



#define KVM_RISCV_BASE_ISA_MASK		GENMASK(25, 0)
@@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(SSAIA),

	KVM_ISA_EXT_ARR(SSCOFPMF),

	KVM_ISA_EXT_ARR(SSTC),

	KVM_ISA_EXT_ARR(SVADE),

	KVM_ISA_EXT_ARR(SVADU),

	KVM_ISA_EXT_ARR(SVINVAL),

	KVM_ISA_EXT_ARR(SVNAPOT),

	KVM_ISA_EXT_ARR(SVPBMT),
@@ -110,6 +113,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_SSCOFPMF:

		/* Sscofpmf depends on interrupt filtering defined in ssaia */

		return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA);

	case KVM_RISCV_ISA_EXT_SVADU:

		/*

		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.

		 * Guest OS can use Svadu only when host OS enable Svadu.

		 */

		return arch_has_hw_pte_young();

	case KVM_RISCV_ISA_EXT_V:

		return riscv_v_vstate_ctrl_user_allowed();

	default:
@@ -181,6 +190,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	/* Extensions which can be disabled using Smstateen */

	case KVM_RISCV_ISA_EXT_SSAIA:

		return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);

	case KVM_RISCV_ISA_EXT_SVADE:

		/*

		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.

		 * Svade is not allowed to disable when the platform use Svade.

		 */

		return arch_has_hw_pte_young();

	default:

		break;

	}