clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos (980d7c84) · Commits · git / linux-net

drivers/clk/qcom/Kconfig

+9 −0

Original line number	Diff line number	Diff line
		@@ -1302,6 +1302,15 @@ config SM_GPUCC_6350
		Say Y if you want to support graphics controller devices and
		functionality such as 3D graphics.

		config SM_GPUCC_MILOS
		tristate "Milos Graphics Clock Controller"
		depends on ARM64 \|\| COMPILE_TEST
		select SM_GCC_MILOS
		help
		Support for the graphics clock controller on Milos devices.
		Say Y if you want to support graphics controller devices and
		functionality such as 3D graphics.

		config SM_GPUCC_8150
		tristate "SM8150 Graphics Clock Controller"
		depends on ARM64 \|\| COMPILE_TEST

drivers/clk/qcom/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -168,6 +168,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
		obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
		obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
		obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
		obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o
		obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
		obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
		obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o

drivers/clk/qcom/gpucc-milos.c

0 → 100644

+562 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
		* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
		*/

		#include <linux/clk-provider.h>
		#include <linux/mod_devicetable.h>
		#include <linux/module.h>
		#include <linux/platform_device.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,milos-gpucc.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-pll.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "clk-regmap-mux.h"
		#include "common.h"
		#include "gdsc.h"
		#include "reset.h"

		/* Need to match the order of clocks in DT binding */
		enum {
		DT_BI_TCXO,
		DT_GPLL0_OUT_MAIN,
		DT_GPLL0_OUT_MAIN_DIV,
		};

		enum {
		P_BI_TCXO,
		P_GPLL0_OUT_MAIN,
		P_GPLL0_OUT_MAIN_DIV,
		P_GPU_CC_PLL0_OUT_EVEN,
		P_GPU_CC_PLL0_OUT_MAIN,
		P_GPU_CC_PLL0_OUT_ODD,
		};

		static const struct pll_vco lucid_ole_vco[] = {
		{ 249600000, 2300000000, 0 },
		};

		/* 700.0 MHz Configuration */
		static const struct alpha_pll_config gpu_cc_pll0_config = {
		.l = 0x24,
		.alpha = 0x7555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x82aa299c,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000003,
		.test_ctl_hi1_val = 0x00009000,
		.test_ctl_hi2_val = 0x00000034,
		.user_ctl_val = 0x00000400,
		.user_ctl_hi_val = 0x00000005,
		};

		static struct clk_alpha_pll gpu_cc_pll0 = {
		.offset = 0x0,
		.config = &gpu_cc_pll0_config,
		.vco_table = lucid_ole_vco,
		.num_vco = ARRAY_SIZE(lucid_ole_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_pll0",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = {
		{ 0x1, 2 },
		{ }
		};

		static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
		.offset = 0x0,
		.post_div_shift = 10,
		.post_div_table = post_div_table_gpu_cc_pll0_out_even,
		.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even),
		.width = 4,
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_pll0_out_even",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_pll0.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
		},
		};

		static const struct parent_map gpu_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_0[] = {
		{ .index = DT_BI_TCXO },
		{ .index = DT_GPLL0_OUT_MAIN },
		{ .index = DT_GPLL0_OUT_MAIN_DIV },
		};

		static const struct parent_map gpu_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
		{ P_GPU_CC_PLL0_OUT_EVEN, 2 },
		{ P_GPU_CC_PLL0_OUT_ODD, 3 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_1[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &gpu_cc_pll0.clkr.hw },
		{ .hw = &gpu_cc_pll0_out_even.clkr.hw },
		{ .hw = &gpu_cc_pll0.clkr.hw },
		{ .index = DT_GPLL0_OUT_MAIN },
		{ .index = DT_GPLL0_OUT_MAIN_DIV },
		};

		static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_ff_clk_src = {
		.cmd_rcgr = 0x9474,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_0,
		.freq_tbl = ftbl_gpu_cc_ff_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_ff_clk_src",
		.parent_data = gpu_cc_parent_data_0,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(350000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
		F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
		F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_gmu_clk_src = {
		.cmd_rcgr = 0x9318,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_1,
		.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gmu_clk_src",
		.parent_data = gpu_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_hub_clk_src = {
		.cmd_rcgr = 0x93ec,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_1,
		.freq_tbl = ftbl_gpu_cc_hub_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_clk_src",
		.parent_data = gpu_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
		.reg = 0x942c,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_branch gpu_cc_ahb_clk = {
		.halt_reg = 0x90bc,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x90bc,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_ahb_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_accu_shift_clk = {
		.halt_reg = 0x910c,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x910c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cx_accu_shift_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_ff_clk = {
		.halt_reg = 0x90ec,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x90ec,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cx_ff_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_ff_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_gmu_clk = {
		.halt_reg = 0x90d4,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x90d4,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cx_gmu_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_gmu_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cxo_clk = {
		.halt_reg = 0x90e4,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x90e4,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cxo_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_dpm_clk = {
		.halt_reg = 0x9110,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9110,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_dpm_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_freq_measure_clk = {
		.halt_reg = 0x900c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x900c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_freq_measure_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_accu_shift_clk = {
		.halt_reg = 0x9070,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x9070,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gx_accu_shift_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = {
		.halt_reg = 0x9068,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9068,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gx_acd_ahb_ff_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_ff_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_gmu_clk = {
		.halt_reg = 0x9060,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9060,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gx_gmu_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_gmu_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = {
		.halt_reg = 0x906c,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x906c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gx_rcg_ahb_ff_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_ff_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
		.halt_reg = 0x7000,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x7000,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hub_aon_clk = {
		.halt_reg = 0x93e8,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x93e8,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_aon_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hub_cx_int_clk = {
		.halt_reg = 0x90e8,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x90e8,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_cx_int_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_memnoc_gfx_clk = {
		.halt_reg = 0x90f4,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x90f4,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_memnoc_gfx_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct gdsc gpu_cc_cx_gdsc = {
		.gdscr = 0x9080,
		.gds_hw_ctrl = 0x9094,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x8,
		.pd = {
		.name = "gpu_cc_cx_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = RETAIN_FF_ENABLE \| VOTABLE,
		};

		static struct clk_regmap *gpu_cc_milos_clocks[] = {
		[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
		[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
		[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
		[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
		[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
		[GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
		[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
		[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
		[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
		[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
		[GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr,
		[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
		[GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr,
		[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
		[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
		[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
		[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
		[GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
		[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
		[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
		[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
		};

		static struct gdsc *gpu_cc_milos_gdscs[] = {
		[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
		};

		static const struct qcom_reset_map gpu_cc_milos_resets[] = {
		[GPU_CC_CB_BCR] = { 0x93a0 },
		[GPU_CC_CX_BCR] = { 0x907c },
		[GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
		[GPU_CC_FF_BCR] = { 0x9470 },
		[GPU_CC_GMU_BCR] = { 0x9314 },
		[GPU_CC_GX_BCR] = { 0x905c },
		[GPU_CC_RBCPR_BCR] = { 0x91e0 },
		[GPU_CC_XO_BCR] = { 0x9000 },
		};

		static struct clk_alpha_pll *gpu_cc_milos_plls[] = {
		&gpu_cc_pll0,
		};

		static u32 gpu_cc_milos_critical_cbcrs[] = {
		0x93a4, /* GPU_CC_CB_CLK */
		0x9008, /* GPU_CC_CXO_AON_CLK */
		0x9010, /* GPU_CC_DEMET_CLK */
		0x9064, /* GPU_CC_GX_AHB_FF_CLK */
		0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */
		0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
		0x90cc, /* GPU_CC_SLEEP_CLK */
		};

		static const struct regmap_config gpu_cc_milos_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x95e8,
		.fast_io = true,
		};

		static struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
		.alpha_plls = gpu_cc_milos_plls,
		.num_alpha_plls = ARRAY_SIZE(gpu_cc_milos_plls),
		.clk_cbcrs = gpu_cc_milos_critical_cbcrs,
		.num_clk_cbcrs = ARRAY_SIZE(gpu_cc_milos_critical_cbcrs),
		};

		static const struct qcom_cc_desc gpu_cc_milos_desc = {
		.config = &gpu_cc_milos_regmap_config,
		.clks = gpu_cc_milos_clocks,
		.num_clks = ARRAY_SIZE(gpu_cc_milos_clocks),
		.resets = gpu_cc_milos_resets,
		.num_resets = ARRAY_SIZE(gpu_cc_milos_resets),
		.gdscs = gpu_cc_milos_gdscs,
		.num_gdscs = ARRAY_SIZE(gpu_cc_milos_gdscs),
		.use_rpm = true,
		.driver_data = &gpu_cc_milos_driver_data,
		};

		static const struct of_device_id gpu_cc_milos_match_table[] = {
		{ .compatible = "qcom,milos-gpucc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, gpu_cc_milos_match_table);

		static int gpu_cc_milos_probe(struct platform_device *pdev)
		{
		return qcom_cc_probe(pdev, &gpu_cc_milos_desc);
		}

		static struct platform_driver gpu_cc_milos_driver = {
		.probe = gpu_cc_milos_probe,
		.driver = {
		.name = "gpu_cc-milos",
		.of_match_table = gpu_cc_milos_match_table,
		},
		};

		module_platform_driver(gpu_cc_milos_driver);

		MODULE_DESCRIPTION("QTI GPU_CC Milos Driver");
		MODULE_LICENSE("GPL");