Commit 980fffd0 authored by Jessica Zhang's avatar Jessica Zhang Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Set input_sel bit for INTF 



Set the input_sel bit for encoders as it was missed in the initial
implementation.

Reported-by: default avatarRob Clark <robdclark@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39


Fixes: 91143873 ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/572007/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent aee797df

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

+1 −1
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 


static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)

{

	dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count);

	dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1);

}



static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 


static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)

{

	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count);

	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);

}



static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

+7 −2
Original line number Diff line number Diff line
@@ -475,9 +475,13 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, 
		      cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);

}



/*

 * note: Aside from encoders, input_sel should be set to 0x0 by default

 */

void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable, u32 frame_count)

		bool enable, u32 frame_count,

		u8 input_sel)

{

	u32 config = 0;
@@ -488,7 +492,8 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, 


	if (enable) {

		config = (frame_count & MISR_FRAME_COUNT_MASK) |

			MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;

			MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |

			((input_sel & 0xF) << 24);



		DPU_REG_WRITE(c, misr_ctrl_offset, config);

	} else {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

+2 −1
Original line number Diff line number Diff line
@@ -363,7 +363,8 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, 
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable,

		u32 frame_count);

		u32 frame_count,

		u8 input_sel);



int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,