Unverified Commit 98266d5f authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'renesas-clk-for-v7.1-tag2' of... 

Merge tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Add SPI clocks and resets on Renesas RZ/G3E
 - Add PCIe clocks and resets on Renesas RZ/V2N, RZ/V2H(P), and RZ/G3E
 - Enable watchdog reset on Renesas RZ/N1D
 - Remove clocks for watchdogs meant for other CPU cores on Renesas RZ/V2N
 - Handle critical clock during system resume on Renesas RZ/G2L, RZ/G2UL, and
   RZ/G3S
 - Add initial support for the Renesas RZ/G3L (R9A08G046) SoC

* tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Add support for RZ/G3L SoC
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  clk: renesas: rzg2l: Re-enable critical module clocks during resume
  clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
  clk: renesas: rzg2l: Add helper for mod clock enable/disable
  clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
  clk: renesas: rzg2l: Add support for critical resets
  clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
  clk: renesas: r9a06g032: Enable watchdog reset sources
  clk: renesas: cpg-mssr: Use struct_size() helper
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  clk: renesas: r9a09g057: Add PCIe clocks and reset
  clk: renesas: r9a09g056: Add PCIe clocks and reset
  clk: renesas: r9a09g047: Add entries for the RSPIs
parents 96df8137 77894661

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+35 −5
Original line number Diff line number Diff line
@@ -28,19 +28,30 @@ properties: 
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a08g045-cpg # RZ/G3S

      - renesas,r9a08g046-cpg # RZ/G3L

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

    maxItems: 1



  clocks:

    maxItems: 1

    minItems: 1

    items:

      - description: Clock source to CPG can be either from external clock

                     input (EXCLK) or crystal oscillator (XIN/XOUT).

      - description: ETH0 TXC clock input

      - description: ETH0 RXC clock input

      - description: ETH1 TXC clock input

      - description: ETH1 RXC clock input



  clock-names:

    description:

      Clock source to CPG can be either from external clock input (EXCLK) or

      crystal oscillator (XIN/XOUT).

    const: extal

    minItems: 1

    items:

      - const: extal

      - const: eth0_txc_tx_clk

      - const: eth0_rxc_rx_clk

      - const: eth1_txc_tx_clk

      - const: eth1_rxc_rx_clk



  '#clock-cells':

    description: |
@@ -74,6 +85,25 @@ required: 
  - '#power-domain-cells'

  - '#reset-cells'



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a08g046-cpg

    then:

      properties:

        clocks:

          minItems: 5

        clock-names:

          minItems: 5

    else:

      properties:

        clocks:

          maxItems: 1

        clock-names:

          maxItems: 1



additionalProperties: false



examples:

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ config CLK_RENESAS 
	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_R9A08G045 if ARCH_R9A08G045

	select CLK_R9A08G046 if ARCH_R9A08G046

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_R9A09G047 if ARCH_R9A09G047

	select CLK_R9A09G056 if ARCH_R9A09G056
@@ -194,6 +195,10 @@ config CLK_R9A08G045 
	bool "RZ/G3S clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A08G046

	bool "RZ/G3L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A09G011

	bool "RZ/V2M clock support" if COMPILE_TEST

	select CLK_RZG2L
@@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL 
	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST

	bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



config CLK_RZV2H

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o 
obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o

obj-$(CONFIG_CLK_R9A08G046)		+= r9a08g046-cpg.o

obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o

obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o

obj-$(CONFIG_CLK_R9A09G056)		+= r9a09g056-cpg.o

drivers/clk/renesas/r9a06g032-clocks.c

+3 −2
Original line number Diff line number Diff line
@@ -1342,8 +1342,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 
	/* Clear potentially pending resets */

	writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,

	       clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);

	/* Allow software reset */

	writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,

	/* Allow watchdog and software resets */

	writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |

	       R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,

	       clocks->reg + R9A06G032_SYSCTRL_RSTEN);



	error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,

drivers/clk/renesas/r9a07g043-cpg.c

+9 −0
Original line number Diff line number Diff line
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A07G043_DMAC_ACLK,

};



static const unsigned int r9a07g043_crit_resets[] = {

	R9A07G043_DMAC_ARESETN,

	R9A07G043_DMAC_RST_ASYNC,

};



#ifdef CONFIG_ARM64

static const unsigned int r9a07g043_no_pm_mod_clks[] = {

	MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { 
	.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */

#endif



	/* Critical Resets */

	.crit_resets = r9a07g043_crit_resets,

	.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),



	.has_clk_mon_regs = true,

};