Commit 9888f736 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Add a noverbose flag to psp_wait_for 



For extended wait with retries on a PSP register value, add a noverbose
flag to avoid excessive error messages on each timeout.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a54e4639

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+8 −5
Original line number Diff line number Diff line
@@ -575,9 +575,11 @@ static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 
	return 0;

}



int psp_wait_for(struct psp_context *psp, uint32_t reg_index,

		 uint32_t reg_val, uint32_t mask, bool check_changed)

int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,

		 uint32_t mask, uint32_t flags)

{

	bool check_changed = flags & PSP_WAITREG_CHANGED;

	bool verbose = !(flags & PSP_WAITREG_NOVERBOSE);

	uint32_t val;

	int i;

	struct amdgpu_device *adev = psp->adev;
@@ -597,6 +599,7 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 
		udelay(1);

	}



	if (verbose)

		dev_err(adev->dev,

			"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",

			reg_index, mask, val, reg_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+5 −2
Original line number Diff line number Diff line
@@ -134,6 +134,9 @@ enum psp_reg_prog_id { 
	PSP_REG_LAST

};



#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */

#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */



struct psp_funcs {

	int (*init_microcode)(struct psp_context *psp);

	int (*wait_for_bootloader)(struct psp_context *psp);
@@ -532,8 +535,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 
extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;

extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;



extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,

			uint32_t field_val, uint32_t mask, bool check_changed);

int psp_wait_for(struct psp_context *psp, uint32_t reg_index,

		 uint32_t field_val, uint32_t mask, uint32_t flags);

extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,

			uint32_t field_val, uint32_t mask, uint32_t msec_timeout);

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

+2 −2
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp, 


	/* Wait for response flag (bit 31) in C2PMSG_64 */

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);



	return ret;

}
@@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp, 


	/* Wait for response flag (bit 31) in C2PMSG_64 */

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);



	return ret;

}

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+17 −18
Original line number Diff line number Diff line
@@ -152,11 +152,9 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 
	for (retry_loop = 0; retry_loop < 10; retry_loop++) {

		/* Wait for bootloader to signify that is

		    ready having bit 31 of C2PMSG_35 set to 1 */

		ret = psp_wait_for(psp,

				   SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

				   0x80000000,

				   0x80000000,

				   false);

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);



		if (ret == 0)

			return 0;
@@ -252,8 +250,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 
	/* there might be handshake issue with hardware which needs delay */

	mdelay(20);

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),

			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),

			   0, true);

			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

			   PSP_WAITREG_CHANGED);



	return ret;

}
@@ -279,11 +277,11 @@ static int psp_v11_0_ring_stop(struct psp_context *psp, 
	if (amdgpu_sriov_vf(adev))

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);

	else

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);



	return ret;

}
@@ -321,13 +319,13 @@ static int psp_v11_0_ring_create(struct psp_context *psp, 
		/* Wait for response flag (bit 31) in C2PMSG_101 */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);



	} else {

		/* Wait for sOS ready for ring creation */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);

			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);

		if (ret) {

			DRM_ERROR("Failed to wait for sOS ready for ring creation\n");

			return ret;
@@ -353,7 +351,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp, 
		/* Wait for response flag (bit 31) in C2PMSG_64 */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);

	}



	return ret;
@@ -387,7 +385,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) 
	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);



	ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,

			   MBOX_TOS_READY_MASK, false);

			   MBOX_TOS_READY_MASK, 0);



	if (ret) {

		DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -402,7 +400,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) 
	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);



	ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,

			   false);

			   0);



	if (ret) {

		DRM_INFO("psp mode 1 reset failed!\n");
@@ -428,8 +426,9 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 


	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;

	for (i = 0; i < max_wait; i++) {

		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

				   0x80000000, 0x80000000, false);

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);

		if (ret == 0)

			break;

	}
@@ -608,7 +607,7 @@ static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc 
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));



	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

			     0x80000000, 0x80000000, false);

			   0x80000000, 0x80000000, 0);

	if (ret)

		return ret;
@@ -645,7 +644,7 @@ static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);



	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

				     0x80000000, 0x80000000, false);

			   0x80000000, 0x80000000, 0);

	if (!ret)

		*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);

drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c

+5 −5
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp, 
		/* Wait for response flag (bit 31) */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);

	} else {

		/* Write the ring destroy command*/

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
@@ -53,7 +53,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp, 
		/* Wait for response flag (bit 31) */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);

	}



	return ret;
@@ -91,13 +91,13 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp, 
		/* Wait for response flag (bit 31) in C2PMSG_101 */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);



	} else {

		/* Wait for sOS ready for ring creation */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);

			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);

		if (ret) {

			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");

			return ret;
@@ -123,7 +123,7 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp, 
		/* Wait for response flag (bit 31) in C2PMSG_64 */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);

			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);

	}



	return ret;