Commit 98a4f5b7 authored by Jani Nurminen's avatar Jani Nurminen Committed by Bjorn Helgaas
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PCI: xilinx-nwl: Fix ECAM programming 



When PCIe has been set up by the bootloader, the ecam_size field in the
E_ECAM_CONTROL register already contains a value.

The driver previously programmed it to 0xc (for 16 busses; 16 MB), but
bumped to 0x10 (for 256 busses; 256 MB) by the commit 2fccd115 ("PCI:
xilinx-nwl: Modify ECAM size to enable support for 256 buses").

Regardless of what the bootloader has programmed, the driver ORs in a
new maximal value without doing a proper RMW sequence. This can lead to
problems.

For example, if the bootloader programs in 0xc and the driver uses 0x10,
the ORed result is 0x1c, which is beyond the ecam_max_size limit of 0x10
(from E_ECAM_CAPABILITIES).

Avoid the problems by doing a proper RMW.

Fixes: 2fccd115 ("PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses")
Signed-off-by: default avatarJani Nurminen <jani.nurminen@windriver.com>
[mani: added stable tag]
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/e83a2af2-af0b-4670-bcf5-ad408571c2b0@windriver.com
parent 8f5ae30d

drivers/pci/controller/pcie-xilinx-nwl.c

+4 −3
Original line number Diff line number Diff line
@@ -718,9 +718,10 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 
	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |

			  E_ECAM_CR_ENABLE, E_ECAM_CONTROL);



	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |

			  (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),

			  E_ECAM_CONTROL);

	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);

	ecam_val &= ~E_ECAM_SIZE_LOC;

	ecam_val |= NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT;

	nwl_bridge_writel(pcie, ecam_val, E_ECAM_CONTROL);



	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),

			  E_ECAM_BASE_LO);