Commit 98bc7682 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

Merge tag 'at91-soc-7.1' of... 

Merge tag 'at91-soc-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers

Microchip AT91 SoC updates for v7.1

This update includes:
- device tree bindings conversion to DT schema for CHIPID, RAM
  controller and PIT, PIT64b, ST timers

* tag 'at91-soc-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux

:
  dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema
  dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
  dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema
  dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema
  dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parents d7dbdada f3ae0049

Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Claudiu Beznea <claudiu.beznea@tuxon.dev>



description:

  The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various

  Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs  manages external

  SDRAM / DDR memory. It is typically exposed as a syscon node for

  register access from other drivers (e.g. for initialization or mode

  configuration). No interrupts or clocks are usually required in the

  binding.



properties:

  compatible:

    oneOf:

      - items:

          - const: atmel,at91rm9200-sdramc

          - const: syscon

      - items:

          - const: microchip,sama7d65-uddrc

          - const: microchip,sama7g5-uddrc

      - enum:

          - atmel,at91sam9260-sdramc

          - atmel,at91sam9g45-ddramc

          - atmel,sama5d3-ddramc

          - microchip,sam9x60-ddramc

          - microchip,sam9x7-ddramc

          - microchip,sama7g5-uddrc



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    items:

      - const: ddrck

      - const: mpddr



required:

  - compatible

  - reg



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/at91.h>

    ramc@ffffe400 {

        compatible = "atmel,at91sam9g45-ddramc";

        reg = <0xffffe400 0x200>;

        clocks = <&pmc PMC_TYPE_SYSTEM 2>;

        clock-names = "ddrck";

    };

...

Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Atmel System Timer



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Claudiu Beznea <claudiu.beznea@tuxon.dev>



description:

  The System Timer (ST) module in AT91RM9200 provides periodic tick and

  alarm capabilities. It is exposed as a simple multi-function device

  (simple-mfd + syscon) because it shares its register space and interrupt

  with other System Controller blocks.



properties:

  compatible:

    items:

      - const: atmel,at91rm9200-st

      - const: syscon

      - const: simple-mfd



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 1



patternProperties:

  "^watchdog@[0-9a-f]+$":

    $ref: /schemas/watchdog/atmel,at91rm9200-wdt.yaml#



required:

  - compatible

  - reg

  - interrupts

  - clocks



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    timer@fffffd00 {

        compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";

        reg = <0xfffffd00 0x100>;

        interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

        clocks = <&slow_xtal>;

        #address-cells = <1>;

        #size-cells = <1>;



        watchdog@fffffd40 {

            compatible = "atmel,at91rm9200-wdt";

            reg = <0xfffffd40 0x40>;

        };

    };

...

Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Atmel AT91SAM9260 Periodic Interval Timer (PIT)



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Claudiu Beznea <claudiu.beznea@tuxon.dev>



description:

  The Periodic Interval Timer (PIT) is part of the System Controller of

  various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series).

  It is a simple down-counter timer used mainly as the kernel tick source.

  The PIT is clocked from the slow clock and shares a single IRQ line with

  other System Controller peripherals.



properties:

  compatible:

    const: atmel,at91sam9260-pit



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    timer@fffffd30 {

        compatible = "atmel,at91sam9260-pit";

        reg = <0xfffffd30 0x10>;

        interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk32k>;

    };

...

Documentation/devicetree/bindings/arm/atmel-sysregs.txt

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Atmel system registers



Chipid required properties:

- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"

			"microchip,sama7d65-chipid"

- reg : Should contain registers location and length



PIT Timer required properties:

- compatible: Should be "atmel,at91sam9260-pit"

- reg: Should contain registers location and length

- interrupts: Should contain interrupt for the PIT which is the IRQ line

  shared across all System Controller members.



PIT64B Timer required properties:

- compatible: Should be "microchip,sam9x60-pit64b" or

			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"

			"microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"

- reg: Should contain registers location and length

- interrupts: Should contain interrupt for PIT64B timer

- clocks: Should contain the available clock sources for PIT64B timer.



System Timer (ST) required properties:

- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"

- reg: Should contain registers location and length

- interrupts: Should contain interrupt for the ST which is the IRQ line

  shared across all System Controller members.

- clocks: phandle to input clock.

Its subnodes can be:

- watchdog: compatible should be "atmel,at91rm9200-wdt"



RAMC SDRAM/DDR Controller required properties:

- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or

			"atmel,at91sam9260-sdramc" or

			"atmel,at91sam9g45-ddramc" or

			"atmel,sama5d3-ddramc" or

			"microchip,sam9x60-ddramc" or

			"microchip,sama7g5-uddrc" or

			"microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or

			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".

- reg: Should contain registers location and length



Examples:



	ramc0: ramc@ffffe800 {

		compatible = "atmel,at91sam9g45-ddramc";

		reg = <0xffffe800 0x200>;

	};

Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PIT64B 64-bit Periodic Interval Timer



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Claudiu Beznea <claudiu.beznea@tuxon.dev>



description:

  The Microchip PIT64B is a 64-bit periodic interval timer used in

  several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and

  SAMA7D65 families. It provides extended timing range, flexible

  clock selection and supports both periodic and one-shot interrupt

  generation modes.



properties:

  compatible:

    oneOf:

      - const: microchip,sam9x60-pit64b

      - items:

          - enum:

              - microchip,sam9x7-pit64b

              - microchip,sama7d65-pit64b

              - microchip,sama7g5-pit64b

          - const: microchip,sam9x60-pit64b



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    maxItems: 2

    items:

      enum:

        - pclk

        - gclk



required:

  - compatible

  - reg

  - interrupts

  - clocks



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/at91.h>

    timer@f0028000 {

        compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";

        reg = <0xf0028000 0x100>;

        interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;

        clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;

        clock-names = "pclk", "gclk";

    };

...