Commit 98ce906b authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

RISC-V: KVM: No need to update the counter value during reset 



The virtual counter value is updated during pmu_ctr_read. There is no need
to update it in reset case. Otherwise, it will be counted twice which is
incorrect.

Fixes: 0cb74b65 ("RISC-V: KVM: Implement perf support without sampling")
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-12-atishp@rivosinc.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 57990ab9

arch/riscv/kvm/vcpu_pmu.c

+2 −6
Original line number Diff line number Diff line
@@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, 
{

	struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);

	int i, pmc_index, sbiret = 0;

	u64 enabled, running;

	struct kvm_pmc *pmc;

	int fevent_code;
@@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, 
				sbiret = SBI_ERR_ALREADY_STOPPED;

			}



			if (flags & SBI_PMU_STOP_FLAG_RESET) {

				/* Relase the counter if this is a reset request */

				pmc->counter_val += perf_event_read_value(pmc->perf_event,

									  &enabled, &running);

			if (flags & SBI_PMU_STOP_FLAG_RESET)

				/* Release the counter if this is a reset request */

				kvm_pmu_release_perf_event(pmc);

			}

		} else {

			sbiret = SBI_ERR_INVALID_PARAM;

		}