Commit 98e5b7f9 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Bjorn Andersson
Browse files

drm/msm/adreno: Setup SMMU aparture for per-process page table 



Support for per-process page tables requires the SMMU aparture to be
setup such that the GPU can make updates with the SMMU. On some targets
this is done statically in firmware, on others it's expected to be
requested in runtime by the driver, through a SCM call.

One place where configuration is expected to be done dynamically is the
QCS6490 rb3gen2.

The downstream driver does this unconditioanlly on any A6xx and newer,
so follow suite and make the call.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: default avatarRob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20241110-adreno-smmu-aparture-v2-2-9b1fb2ee41d4@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 1af75b2a

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+11 −0
Original line number Diff line number Diff line
@@ -572,8 +572,19 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 


int adreno_hw_init(struct msm_gpu *gpu)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	int ret;



	VERB("%s", gpu->name);



	if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&

	    qcom_scm_set_gpu_smmu_aperture_is_available()) {

		/* We currently always use context bank 0, so hard code this */

		ret = qcom_scm_set_gpu_smmu_aperture(0);

		if (ret)

			DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);

	}



	for (int i = 0; i < gpu->nr_rings; i++) {

		struct msm_ringbuffer *ring = gpu->rb[i];