Commit 98e8f2c0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-platform-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Ingo Molnar:
 "This adds support for the AMD hardware feedback interface (HFI), by
  Perry Yuan"

* tag 'x86-platform-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/itmt: Add debugfs file to show core priorities
  platform/x86/amd: hfi: Add debugfs support
  platform/x86/amd: hfi: Set ITMT priority from ranking data
  cpufreq/amd-pstate: Disable preferred cores on designs with workload classification
  x86/process: Clear hardware feedback history for AMD processors
  platform/x86: hfi: Add power management callback
  platform/x86: hfi: Add online and offline callback support
  platform/x86: hfi: Init per-cpu scores for each class
  platform/x86: hfi: Parse CPU core ranking data from shared memory
  platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver
  x86/msr-index: Add AMD workload classification MSRs
  MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver
  Documentation/x86: Add AMD Hardware Feedback Interface documentation
parents e12ac84a f1268214

Documentation/arch/x86/amd-hfi.rst

0 → 100644
+133 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0



======================================================================

Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform

======================================================================



:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved.



:Author: Perry Yuan <perry.yuan@amd.com>

:Author: Mario Limonciello <mario.limonciello@amd.com>



Overview

--------



AMD Heterogeneous Core implementations are comprised of more than one

architectural class and CPUs are comprised of cores of various efficiency and

power capabilities: performance-oriented *classic cores* and power-efficient

*dense cores*. As such, power management strategies must be designed to

accommodate the complexities introduced by incorporating different core types.

Heterogeneous systems can also extend to more than two architectural classes

as well. The purpose of the scheduling feedback mechanism is to provide

information to the operating system scheduler in real time such that the

scheduler can direct threads to the optimal core.



The goal of AMD's heterogeneous architecture is to attain power benefit by

sending background threads to the dense cores while sending high priority

threads to the classic cores. From a performance perspective, sending

background threads to dense cores can free up power headroom and allow the

classic cores to optimally service demanding threads. Furthermore, the area

optimized nature of the dense cores allows for an increasing number of

physical cores. This improved core density will have positive multithreaded

performance impact.



AMD Heterogeneous Core Driver

-----------------------------



The ``amd_hfi`` driver delivers the operating system a performance and energy

efficiency capability data for each CPU in the system. The scheduler can use

the ranking data from the HFI driver to make task placement decisions.



Thread Classification and Ranking Table Interaction

----------------------------------------------------



The thread classification is used to select into a ranking table that

describes an efficiency and performance ranking for each classification.



Threads are classified during runtime into enumerated classes. The classes

represent thread performance/power characteristics that may benefit from

special scheduling behaviors. The below table depicts an example of thread

classification and a preference where a given thread should be scheduled

based on its thread class. The real time thread classification is consumed

by the operating system and is used to inform the scheduler of where the

thread should be placed.



Thread Classification Example Table

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

+----------+----------------+-------------------------------+---------------------+---------+

| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter |

+----------+----------------+-------------------------------+---------------------+---------+

| 0        | Default        | Performant                    | Highest             |         |

+----------+----------------+-------------------------------+---------------------+---------+

| 1        | Non-scalable   | Efficient                     | Lowest              | PMCx1A1 |

+----------+----------------+-------------------------------+---------------------+---------+

| 2        | I/O bound      | Efficient                     | Lowest              | PMCx044 |

+----------+----------------+-------------------------------+---------------------+---------+



Thread classification is performed by the hardware each time that the thread is switched out.

Threads that don't meet any hardware specified criteria are classified as "default".



AMD Hardware Feedback Interface

--------------------------------



The Hardware Feedback Interface provides to the operating system information

about the performance and energy efficiency of each CPU in the system. Each

capability is given as a unit-less quantity in the range [0-255]. A higher

performance value indicates higher performance capability, and a higher

efficiency value indicates more efficiency. Energy efficiency and performance

are reported in separate capabilities in the shared memory based ranking table.



These capabilities may change at runtime as a result of changes in the

operating conditions of the system or the action of external factors.

Power Management firmware is responsible for detecting events that require

a reordering of the performance and efficiency ranking. Table updates happen

relatively infrequently and occur on the time scale of seconds or more.



The following events trigger a table update:

    * Thermal Stress Events

    * Silent Compute

    * Extreme Low Battery Scenarios



The kernel or a userspace policy daemon can use these capabilities to modify

task placement decisions. For instance, if either the performance or energy

capabilities of a given logical processor becomes zero, it is an indication

that the hardware recommends to the operating system to not schedule any tasks

on that processor for performance or energy efficiency reasons, respectively.



Implementation details for Linux

--------------------------------



The implementation of threads scheduling consists of the following steps:



1. A thread is spawned and scheduled to the ideal core using the default

   heterogeneous scheduling policy.

2. The processor profiles thread execution and assigns an enumerated

   classification ID.

   This classification is communicated to the OS via logical processor

   scope MSR.

3. During the thread context switch out the operating system consumes the

   workload (WL) classification which resides in a logical processor scope MSR.

4. The OS triggers the hardware to clear its history by writing to an MSR,

   after consuming the WL classification and before switching in the new thread.

5. If due to the classification, ranking table, and processor availability,

   the thread is not on its ideal processor, the OS will then consider

   scheduling the thread on its ideal processor (if available).



Ranking Table

-------------

The ranking table is a shared memory region that is used to communicate the

performance and energy efficiency capabilities of each CPU in the system.



The ranking table design includes rankings for each APIC ID in the system and

rankings both for performance and efficiency for each workload classification.



.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c

   :doc: amd_shmem_info



Ranking Table update

---------------------------

The power management firmware issues an platform interrupt after updating the

ranking table and is ready for the operating system to consume it. CPUs receive

such interrupt and read new ranking table from shared memory which PCCT table

has provided, then ``amd_hfi`` driver parses the new table to provide new

consume data for scheduling decisions.

Documentation/arch/x86/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ x86-specific Documentation 
   amd-debugging

   amd-memory-encryption

   amd_hsmp

   amd-hfi

   tdx

   pti

   mds

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -1115,6 +1115,15 @@ F: arch/x86/include/asm/amd/hsmp.h 
F:	arch/x86/include/uapi/asm/amd_hsmp.h

F:	drivers/platform/x86/amd/hsmp/









AMD HETERO CORE HARDWARE FEEDBACK DRIVER









M:	Mario Limonciello <mario.limonciello@amd.com>









R:	Perry Yuan <perry.yuan@amd.com>









L:	platform-driver-x86@vger.kernel.org









S:	Supported









B:	https://gitlab.freedesktop.org/drm/amd/-/issues









F:	Documentation/arch/x86/amd-hfi.rst









F:	drivers/platform/x86/amd/hfi/

















AMD IOMMU (AMD-VI)









M:	Joerg Roedel <joro@8bytes.org>









R:	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
































arch/x86/include/asm/msr-index.h



+5
−0






























Original line number
Diff line number
Diff line







@@ -733,6 +733,11 @@







#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301









#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302



















/* AMD Hardware Feedback Support MSRs */









#define MSR_AMD_WORKLOAD_CLASS_CONFIG		0xc0000500









#define MSR_AMD_WORKLOAD_CLASS_ID		0xc0000501









#define MSR_AMD_WORKLOAD_HRST			0xc0000502



















/* AMD Last Branch Record MSRs */









#define MSR_AMD64_LBR_SELECT			0xc000010e










































arch/x86/kernel/itmt.c



+23
−0






























Original line number
Diff line number
Diff line







@@ -59,6 +59,18 @@ static ssize_t sched_itmt_enabled_write(struct file *filp,







	return result;









}



















static int sched_core_priority_show(struct seq_file *s, void *unused)









{









	int cpu;



















	seq_puts(s, "CPU #\tPriority\n");









	for_each_possible_cpu(cpu)









		seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu));



















	return 0;









}









DEFINE_SHOW_ATTRIBUTE(sched_core_priority);



















static const struct file_operations dfs_sched_itmt_fops = {









	.read =         debugfs_read_file_bool,









	.write =        sched_itmt_enabled_write,








@@ -67,6 +79,7 @@ static const struct file_operations dfs_sched_itmt_fops = {







};



















static struct dentry *dfs_sched_itmt;









static struct dentry *dfs_sched_core_prio;



















/**









 * sched_set_itmt_support() - Indicate platform supports ITMT








@@ -102,6 +115,14 @@ int sched_set_itmt_support(void)







		return -ENOMEM;









	}



















	dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644,









						  arch_debugfs_dir, NULL,









						  &sched_core_priority_fops);









	if (IS_ERR_OR_NULL(dfs_sched_core_prio)) {









		dfs_sched_core_prio = NULL;









		return -ENOMEM;









	}



















	sched_itmt_capable = true;



















	sysctl_sched_itmt_enabled = 1;








@@ -133,6 +154,8 @@ void sched_clear_itmt_support(void)

















	debugfs_remove(dfs_sched_itmt);









	dfs_sched_itmt = NULL;









	debugfs_remove(dfs_sched_core_prio);









	dfs_sched_core_prio = NULL;



















	if (sysctl_sched_itmt_enabled) {









		/* disable sched_itmt if we are no longer ITMT capable */