Commit 993fcc40 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: set additional bits on CP halt 



Need to set the pipe reset and cache invalidation bits
on halt otherwise we can get stale state if the CP firmware
changes (e.g., on module unload and reload).

Reviewed-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 37b99322

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+18 −1
Original line number Diff line number Diff line
@@ -3184,6 +3184,15 @@ static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
{

	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);



	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
@@ -3393,7 +3402,15 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 
		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);

	} else {

		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,

			(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

				 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK |

				  CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK |

				  CP_MEC_CNTL__MEC_ME1_HALT_MASK |

				  CP_MEC_CNTL__MEC_ME2_HALT_MASK));

		adev->gfx.kiq[0].ring.sched.ready = false;

	}

	udelay(50);