perf vendor events arm64: Add N3 events/metrics (994256a7) · Commits · git / linux-net

tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/bus.json

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		[
		{
		"ArchStdEvent": "BUS_ACCESS",
		"PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually."
		},
		{
		"ArchStdEvent": "BUS_CYCLES",
		"PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES."
		},
		{
		"ArchStdEvent": "BUS_ACCESS_RD",
		"PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually."
		},
		{
		"ArchStdEvent": "BUS_ACCESS_WR",
		"PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually."
		}
		]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/exception.json

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		[
		{
		"ArchStdEvent": "EXC_TAKEN",
		"PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally."
		},
		{
		"ArchStdEvent": "EXC_RETURN",
		"PublicDescription": "Counts any architecturally executed exception return instructions. For example: AArch64: ERET"
		},
		{
		"ArchStdEvent": "EXC_UNDEF",
		"PublicDescription": "Counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED. Attempting to execute instruction bit patterns that have not been allocated. Attempting to execute instructions when they are disabled. Attempting to execute instructions at an inappropriate Exception level. Attempting to execute an instruction when the value of PSTATE.IL is 1."
		},
		{
		"ArchStdEvent": "EXC_SVC",
		"PublicDescription": "Counts SVC exceptions taken locally."
		},
		{
		"ArchStdEvent": "EXC_PABORT",
		"PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instruction Aborts."
		},
		{
		"ArchStdEvent": "EXC_DABORT",
		"PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, interrupts from the nSEI inputs and internally generated SErrors."
		},
		{
		"ArchStdEvent": "EXC_IRQ",
		"PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are taken locally."
		},
		{
		"ArchStdEvent": "EXC_FIQ",
		"PublicDescription": "Counts FIQ exceptions including the virtual FIQs that are taken locally."
		},
		{
		"ArchStdEvent": "EXC_SMC",
		"PublicDescription": "Counts SMC exceptions take to EL3."
		},
		{
		"ArchStdEvent": "EXC_HVC",
		"PublicDescription": "Counts HVC exceptions taken to EL2."
		},
		{
		"ArchStdEvent": "EXC_TRAP_PABORT",
		"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC."
		},
		{
		"ArchStdEvent": "EXC_TRAP_DABORT",
		"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data Aborts or SError interrupts. Conditions that could cause those exceptions are:\n\n1. Attempting to read or write memory where the MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Interrupts from the SEI input.\n4. internally generated SErrors."
		},
		{
		"ArchStdEvent": "EXC_TRAP_OTHER",
		"PublicDescription": "Counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, data aborts, Instruction Aborts, or interrupts."
		},
		{
		"ArchStdEvent": "EXC_TRAP_IRQ",
		"PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are not taken locally."
		},
		{
		"ArchStdEvent": "EXC_TRAP_FIQ",
		"PublicDescription": "Counts FIQs which are not taken locally but taken from EL0, EL1,\n or EL2 to EL3 (which would be the normal behavior for FIQs when not executing\n in EL3)."
		}
		]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/fp_operation.json

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		[
		{
		"ArchStdEvent": "FP_HP_SPEC",
		"PublicDescription": "Counts speculatively executed half precision floating point operations."
		},
		{
		"ArchStdEvent": "FP_SP_SPEC",
		"PublicDescription": "Counts speculatively executed single precision floating point operations."
		},
		{
		"ArchStdEvent": "FP_DP_SPEC",
		"PublicDescription": "Counts speculatively executed double precision floating point operations."
		},
		{
		"ArchStdEvent": "FP_SCALE_OPS_SPEC",
		"PublicDescription": "Counts speculatively executed scalable single precision floating point operations."
		},
		{
		"ArchStdEvent": "FP_FIXED_OPS_SPEC",
		"PublicDescription": "Counts speculatively executed non-scalable single precision floating point operations."
		}
		]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/general.json

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		[
		{
		"ArchStdEvent": "CPU_CYCLES",
		"PublicDescription": "Counts CPU clock cycles (not timer cycles). The clock measured by this event is defined as the physical clock driving the CPU logic."
		},
		{
		"ArchStdEvent": "CNT_CYCLES",
		"PublicDescription": "Increments at a constant frequency equal to the rate of increment of the System Counter, CNTPCT_EL0."
		}
		]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1d_cache.json

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		[
		{
		"ArchStdEvent": "L1D_CACHE_REFILL",
		"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line."
		},
		{
		"ArchStdEvent": "L1D_CACHE",
		"PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted."
		},
		{
		"ArchStdEvent": "L1D_CACHE_WB",
		"PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode."
		},
		{
		"ArchStdEvent": "L1D_CACHE_LMISS_RD",
		"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read operations, that incurred additional latency."
		},
		{
		"ArchStdEvent": "L1D_CACHE_RD",
		"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access."
		},
		{
		"ArchStdEvent": "L1D_CACHE_WR",
		"PublicDescription": "Counts level 1 data cache accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by virtual address) instruction. Near atomic operations that resolve in the CPUs caches count as a write access and read access."
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_INNER",
		"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches inside the immediate cluster of the core."
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
		"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from outside the immediate cluster of the core, like an SLC in the system interconnect or DRAM."
		},
		{
		"ArchStdEvent": "L1D_CACHE_INVAL",
		"PublicDescription": "Counts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coherency operations from another CPU in the system.\n\nThis event does not count for the following conditions:\n\n1. A cache refill invalidates a cache line.\n2. A CMO which is executed on that CPU and invalidates a cache line specified by set/way.\n\nNote that CMOs that operate by set/way cannot be broadcast from one CPU to another."
		},
		{
		"ArchStdEvent": "L1D_CACHE_RW",
		"PublicDescription": "Counts level 1 data demand cache accesses from any load or store operation. Near atomic operations that resolve in the CPUs caches counts as both a write access and read access."
		},
		{
		"ArchStdEvent": "L1D_CACHE_HWPRF",
		"PublicDescription": "Counts level 1 data cache accesses from any load/store operations generated by the hardware prefetcher."
		},
		{
		"ArchStdEvent": "L1D_CACHE_REFILL_HWPRF",
		"PublicDescription": "Counts level 1 data cache refills where the cache line is requested by a hardware prefetcher."
		}
		]