Commit 9973ac9f authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: Remove unnecessary ice_is_e8xx() functions 



Remove unnecessary ice_is_e8xx() functions and PHY model. Instead, use
MAC type where applicable.

Don't check device type in ice_ptp_maybe_trigger_tx_interrupt(), because
in reality it depends on the ready bitmap, which only E810 does not
have.

Call ice_ptp_cfg_phy_interrupt() unconditionally, because all further
function calls check the MAC type anyway and this allows simpler code
in the future with addition of the new MAC types.

Reorder ICE_MAC_* cases in switches in ice_ptp* as in enum ice_mac_type.

Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent e2c6737e

drivers/net/ethernet/intel/ice/ice.h

+0 −5
Original line number Diff line number Diff line
@@ -1046,10 +1046,5 @@ static inline void ice_clear_rdma_cap(struct ice_pf *pf) 
	clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);

}



static inline enum ice_phy_model ice_get_phy_model(const struct ice_hw *hw)

{

	return hw->ptp.phy_model;

}



extern const struct xdp_metadata_ops ice_xdp_md_ops;

#endif /* _ICE_H_ */

drivers/net/ethernet/intel/ice/ice_common.c

+2 −116
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ static int ice_set_mac_type(struct ice_hw *hw) 
 * ice_is_generic_mac - check if device's mac_type is generic

 * @hw: pointer to the hardware structure

 *

 * Return: true if mac_type is generic (with SBQ support), false if not

 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise.

 */

bool ice_is_generic_mac(struct ice_hw *hw)

{
@@ -194,120 +194,6 @@ bool ice_is_generic_mac(struct ice_hw *hw) 
		hw->mac_type == ICE_MAC_GENERIC_3K_E825);

}



/**

 * ice_is_e810

 * @hw: pointer to the hardware structure

 *

 * returns true if the device is E810 based, false if not.

 */

bool ice_is_e810(struct ice_hw *hw)

{

	return hw->mac_type == ICE_MAC_E810;

}



/**

 * ice_is_e810t

 * @hw: pointer to the hardware structure

 *

 * returns true if the device is E810T based, false if not.

 */

bool ice_is_e810t(struct ice_hw *hw)

{

	switch (hw->device_id) {

	case ICE_DEV_ID_E810C_SFP:

		switch (hw->subsystem_device_id) {

		case ICE_SUBDEV_ID_E810T:

		case ICE_SUBDEV_ID_E810T2:

		case ICE_SUBDEV_ID_E810T3:

		case ICE_SUBDEV_ID_E810T4:

		case ICE_SUBDEV_ID_E810T6:

		case ICE_SUBDEV_ID_E810T7:

			return true;

		}

		break;

	case ICE_DEV_ID_E810C_QSFP:

		switch (hw->subsystem_device_id) {

		case ICE_SUBDEV_ID_E810T2:

		case ICE_SUBDEV_ID_E810T3:

		case ICE_SUBDEV_ID_E810T5:

			return true;

		}

		break;

	default:

		break;

	}



	return false;

}



/**

 * ice_is_e822 - Check if a device is E822 family device

 * @hw: pointer to the hardware structure

 *

 * Return: true if the device is E822 based, false if not.

 */

bool ice_is_e822(struct ice_hw *hw)

{

	switch (hw->device_id) {

	case ICE_DEV_ID_E822C_BACKPLANE:

	case ICE_DEV_ID_E822C_QSFP:

	case ICE_DEV_ID_E822C_SFP:

	case ICE_DEV_ID_E822C_10G_BASE_T:

	case ICE_DEV_ID_E822C_SGMII:

	case ICE_DEV_ID_E822L_BACKPLANE:

	case ICE_DEV_ID_E822L_SFP:

	case ICE_DEV_ID_E822L_10G_BASE_T:

	case ICE_DEV_ID_E822L_SGMII:

		return true;

	default:

		return false;

	}

}



/**

 * ice_is_e823

 * @hw: pointer to the hardware structure

 *

 * returns true if the device is E823-L or E823-C based, false if not.

 */

bool ice_is_e823(struct ice_hw *hw)

{

	switch (hw->device_id) {

	case ICE_DEV_ID_E823L_BACKPLANE:

	case ICE_DEV_ID_E823L_SFP:

	case ICE_DEV_ID_E823L_10G_BASE_T:

	case ICE_DEV_ID_E823L_1GBE:

	case ICE_DEV_ID_E823L_QSFP:

	case ICE_DEV_ID_E823C_BACKPLANE:

	case ICE_DEV_ID_E823C_QSFP:

	case ICE_DEV_ID_E823C_SFP:

	case ICE_DEV_ID_E823C_10G_BASE_T:

	case ICE_DEV_ID_E823C_SGMII:

		return true;

	default:

		return false;

	}

}



/**

 * ice_is_e825c - Check if a device is E825C family device

 * @hw: pointer to the hardware structure

 *

 * Return: true if the device is E825-C based, false if not.

 */

bool ice_is_e825c(struct ice_hw *hw)

{

	switch (hw->device_id) {

	case ICE_DEV_ID_E825C_BACKPLANE:

	case ICE_DEV_ID_E825C_QSFP:

	case ICE_DEV_ID_E825C_SFP:

	case ICE_DEV_ID_E825C_SGMII:

		return true;

	default:

		return false;

	}

}



/**

 * ice_is_pf_c827 - check if pf contains c827 phy

 * @hw: pointer to the hw struct
@@ -2408,7 +2294,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
	info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);

	info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);



	if (!ice_is_e825c(hw)) {

	if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) {

		info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);

		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);

	} else {

drivers/net/ethernet/intel/ice/ice_common.h

+0 −5
Original line number Diff line number Diff line
@@ -131,7 +131,6 @@ int 
ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,

			struct ice_sq_cd *cd);

bool ice_is_generic_mac(struct ice_hw *hw);

bool ice_is_e810(struct ice_hw *hw);

int ice_clear_pf_cfg(struct ice_hw *hw);

int

ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
@@ -276,10 +275,6 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 
void

ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,

		  u64 *prev_stat, u64 *cur_stat);

bool ice_is_e810t(struct ice_hw *hw);

bool ice_is_e822(struct ice_hw *hw);

bool ice_is_e823(struct ice_hw *hw);

bool ice_is_e825c(struct ice_hw *hw);

int

ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,

		     struct ice_aqc_txsched_elem_data *buf);

drivers/net/ethernet/intel/ice/ice_ddp.c

+2 −2
Original line number Diff line number Diff line
@@ -2345,14 +2345,14 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size, 
			cmd->set_flags |= ICE_AQC_TX_TOPO_FLAGS_SRC_RAM |

					  ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW;



		if (ice_is_e825c(hw))

		if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)

			desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);

	} else {

		ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo);

		cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM;

	}



	if (!ice_is_e825c(hw))

	if (hw->mac_type != ICE_MAC_GENERIC_3K_E825)

		desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);



	status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);

drivers/net/ethernet/intel/ice/ice_ptp.c

+69 −64
Original line number Diff line number Diff line
@@ -1318,20 +1318,20 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port) 
	struct ice_hw *hw = &pf->hw;

	int err;



	if (ice_is_e810(hw))

		return 0;



	mutex_lock(&ptp_port->ps_lock);



	switch (ice_get_phy_model(hw)) {

	case ICE_PHY_ETH56G:

		err = ice_stop_phy_timer_eth56g(hw, port, true);

	switch (hw->mac_type) {

	case ICE_MAC_E810:

		err = 0;

		break;

	case ICE_PHY_E82X:

	case ICE_MAC_GENERIC:

		kthread_cancel_delayed_work_sync(&ptp_port->ov_work);



		err = ice_stop_phy_timer_e82x(hw, port, true);

		break;

	case ICE_MAC_GENERIC_3K_E825:

		err = ice_stop_phy_timer_eth56g(hw, port, true);

		break;

	default:

		err = -ENODEV;

	}
@@ -1361,19 +1361,16 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port) 
	unsigned long flags;

	int err;



	if (ice_is_e810(hw))

		return 0;



	if (!ptp_port->link_up)

		return ice_ptp_port_phy_stop(ptp_port);



	mutex_lock(&ptp_port->ps_lock);



	switch (ice_get_phy_model(hw)) {

	case ICE_PHY_ETH56G:

		err = ice_start_phy_timer_eth56g(hw, port);

	switch (hw->mac_type) {

	case ICE_MAC_E810:

		err = 0;

		break;

	case ICE_PHY_E82X:

	case ICE_MAC_GENERIC:

		/* Start the PHY timer in Vernier mode */

		kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
@@ -1398,6 +1395,9 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port) 
		kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work,

					   0);

		break;

	case ICE_MAC_GENERIC_3K_E825:

		err = ice_start_phy_timer_eth56g(hw, port);

		break;

	default:

		err = -ENODEV;

	}
@@ -1432,12 +1432,13 @@ void ice_ptp_link_change(struct ice_pf *pf, bool linkup) 
	/* Skip HW writes if reset is in progress */

	if (pf->hw.reset_ongoing)

		return;

	switch (ice_get_phy_model(hw)) {

	case ICE_PHY_E810:



	switch (hw->mac_type) {

	case ICE_MAC_E810:

		/* Do not reconfigure E810 PHY */

		return;

	case ICE_PHY_ETH56G:

	case ICE_PHY_E82X:

	case ICE_MAC_GENERIC:

	case ICE_MAC_GENERIC_3K_E825:

		ice_ptp_port_phy_restart(ptp_port);

		return;

	default:
@@ -1465,46 +1466,44 @@ static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold) 


	ice_ptp_reset_ts_memory(hw);



	switch (ice_get_phy_model(hw)) {

	case ICE_PHY_ETH56G: {

		int port;

	switch (hw->mac_type) {

	case ICE_MAC_E810:

		return 0;

	case ICE_MAC_GENERIC: {

		int quad;



		for (port = 0; port < hw->ptp.num_lports; port++) {

		for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);

		     quad++) {

			int err;



			err = ice_phy_cfg_intr_eth56g(hw, port, ena, threshold);

			err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);

			if (err) {

				dev_err(dev, "Failed to configure PHY interrupt for port %d, err %d\n",

					port, err);

				dev_err(dev, "Failed to configure PHY interrupt for quad %d, err %d\n",

					quad, err);

				return err;

			}

		}



		return 0;

	}

	case ICE_PHY_E82X: {

		int quad;

	case ICE_MAC_GENERIC_3K_E825: {

		int port;



		for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);

		     quad++) {

		for (port = 0; port < hw->ptp.num_lports; port++) {

			int err;



			err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);

			err = ice_phy_cfg_intr_eth56g(hw, port, ena, threshold);

			if (err) {

				dev_err(dev, "Failed to configure PHY interrupt for quad %d, err %d\n",

					quad, err);

				dev_err(dev, "Failed to configure PHY interrupt for port %d, err %d\n",

					port, err);

				return err;

			}

		}



		return 0;

	}

	case ICE_PHY_E810:

		return 0;

	case ICE_PHY_UNSUP:

	case ICE_MAC_UNKNOWN:

	default:

		dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,

			 ice_get_phy_model(hw));

		return -EOPNOTSUPP;

	}

}
@@ -1740,7 +1739,7 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, 
	/* 0. Reset mode & out_en in AUX_OUT */

	wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);



	if (ice_is_e825c(hw)) {

	if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) {

		int err;



		/* Enable/disable CGU 1PPS output for E825C */
@@ -1824,7 +1823,7 @@ static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, 
		return ice_ptp_write_perout(hw, rq->index, gpio_pin, 0, 0);



	if (strncmp(pf->ptp.pin_desc[pin_desc_idx].name, "1PPS", 64) == 0 &&

	    period != NSEC_PER_SEC && hw->ptp.phy_model == ICE_PHY_E82X) {

	    period != NSEC_PER_SEC && hw->mac_type == ICE_MAC_GENERIC) {

		dev_err(ice_pf_to_dev(pf), "1PPS pin supports only 1 s period\n");

		return -EOPNOTSUPP;

	}
@@ -2078,7 +2077,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) 
	/* For Vernier mode on E82X, we need to recalibrate after new settime.

	 * Start with marking timestamps as invalid.

	 */

	if (ice_get_phy_model(hw) == ICE_PHY_E82X) {

	if (hw->mac_type == ICE_MAC_GENERIC) {

		err = ice_ptp_clear_phy_offset_ready_e82x(hw);

		if (err)

			dev_warn(ice_pf_to_dev(pf), "Failed to mark timestamps as invalid before settime\n");
@@ -2102,7 +2101,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) 
	ice_ptp_enable_all_perout(pf);



	/* Recalibrate and re-enable timestamp blocks for E822/E823 */

	if (ice_get_phy_model(hw) == ICE_PHY_E82X)

	if (hw->mac_type == ICE_MAC_GENERIC)

		ice_ptp_restart_all_phy(pf);

exit:

	if (err) {
@@ -2556,7 +2555,7 @@ static void ice_ptp_set_funcs_e82x(struct ice_pf *pf) 
		pf->ptp.info.getcrosststamp = ice_ptp_getcrosststamp_e82x;



#endif /* CONFIG_ICE_HWTS */

	if (ice_is_e825c(&pf->hw)) {

	if (pf->hw.mac_type == ICE_MAC_GENERIC_3K_E825) {

		pf->ptp.ice_pin_desc = ice_pin_desc_e825c;

		pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e825c);

	} else {
@@ -2644,10 +2643,17 @@ static void ice_ptp_set_caps(struct ice_pf *pf) 
	info->enable = ice_ptp_gpio_enable;

	info->verify = ice_verify_pin;



	if (ice_is_e810(&pf->hw))

	switch (pf->hw.mac_type) {

	case ICE_MAC_E810:

		ice_ptp_set_funcs_e810(pf);

	else

		return;

	case ICE_MAC_GENERIC:

	case ICE_MAC_GENERIC_3K_E825:

		ice_ptp_set_funcs_e82x(pf);

		return;

	default:

		return;

	}

}



/**
@@ -2777,7 +2783,7 @@ static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf) 
	bool trigger_oicr = false;

	unsigned int i;



	if (ice_is_e810(hw))

	if (!pf->ptp.port.tx.has_ready_bitmap)

		return;



	if (!ice_pf_src_tmr_owned(pf))
@@ -2912,14 +2918,12 @@ static int ice_ptp_rebuild_owner(struct ice_pf *pf) 
	 */

	ice_ptp_flush_all_tx_tracker(pf);



	if (!ice_is_e810(hw)) {

	/* Enable quad interrupts */

	err = ice_ptp_cfg_phy_interrupt(pf, true, 1);

	if (err)

		return err;



	ice_ptp_restart_all_phy(pf);

	}



	/* Re-enable all periodic outputs and external timestamp events */

	ice_ptp_enable_all_perout(pf);
@@ -2971,8 +2975,9 @@ void ice_ptp_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type) 


static bool ice_is_primary(struct ice_hw *hw)

{

	return ice_is_e825c(hw) && ice_is_dual(hw) ?

		!!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) : true;

	return hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) ?

		       !!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) :

		       true;

}



static int ice_ptp_setup_adapter(struct ice_pf *pf)
@@ -2990,7 +2995,7 @@ static int ice_ptp_setup_pf(struct ice_pf *pf) 
	struct ice_ptp *ctrl_ptp = ice_get_ctrl_ptp(pf);

	struct ice_ptp *ptp = &pf->ptp;



	if (WARN_ON(!ctrl_ptp) || ice_get_phy_model(&pf->hw) == ICE_PHY_UNSUP)

	if (WARN_ON(!ctrl_ptp) || pf->hw.mac_type == ICE_MAC_UNKNOWN)

		return -ENODEV;



	INIT_LIST_HEAD(&ptp->port.list_node);
@@ -3007,7 +3012,7 @@ static void ice_ptp_cleanup_pf(struct ice_pf *pf) 
{

	struct ice_ptp *ptp = &pf->ptp;



	if (ice_get_phy_model(&pf->hw) != ICE_PHY_UNSUP) {

	if (pf->hw.mac_type != ICE_MAC_UNKNOWN) {

		mutex_lock(&pf->adapter->ports.lock);

		list_del(&ptp->port.list_node);

		mutex_unlock(&pf->adapter->ports.lock);
@@ -3134,18 +3139,18 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port) 


	mutex_init(&ptp_port->ps_lock);



	switch (ice_get_phy_model(hw)) {

	case ICE_PHY_ETH56G:

		return ice_ptp_init_tx_eth56g(pf, &ptp_port->tx,

					      ptp_port->port_num);

	case ICE_PHY_E810:

	switch (hw->mac_type) {

	case ICE_MAC_E810:

		return ice_ptp_init_tx_e810(pf, &ptp_port->tx);

	case ICE_PHY_E82X:

	case ICE_MAC_GENERIC:

		kthread_init_delayed_work(&ptp_port->ov_work,

					  ice_ptp_wait_for_offsets);



		return ice_ptp_init_tx_e82x(pf, &ptp_port->tx,

					    ptp_port->port_num);

	case ICE_MAC_GENERIC_3K_E825:

		return ice_ptp_init_tx_eth56g(pf, &ptp_port->tx,

					      ptp_port->port_num);

	default:

		return -ENODEV;

	}
@@ -3162,8 +3167,8 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port) 
 */

static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)

{

	switch (ice_get_phy_model(&pf->hw)) {

	case ICE_PHY_E82X:

	switch (pf->hw.mac_type) {

	case ICE_MAC_GENERIC:

		/* E822 based PHY has the clock owner process the interrupt

		 * for all ports.

		 */