Commit 99831ab9 authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy Committed by Imre Deak
Browse files

drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info 



Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.

This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.

v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
      accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)

Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-31-imre.deak@intel.com
parent 3a5f80e4

drivers/gpu/drm/i915/display/intel_dp.c

+12 −8
Original line number Diff line number Diff line
@@ -1811,7 +1811,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec 
	return 0;

}



static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)

int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)

{

	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */

	switch (pipe_config->output_format) {
@@ -1828,7 +1828,7 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) 
	return 0;

}



static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector,

int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,

					 struct intel_crtc_state *pipe_config,

					 int bpc)

{
@@ -1944,12 +1944,14 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 
	int dsc_joiner_max_bpp;



	dsc_src_min_bpp = dsc_src_min_compressed_bpp();

	dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);

	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);

	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);

	dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));



	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);

	dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);

	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,

								pipe_config,

								pipe_bpp / 3);

	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;



	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
@@ -2104,12 +2106,14 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 
	pipe_config->lane_count = limits->max_lane_count;



	dsc_src_min_bpp = dsc_src_min_compressed_bpp();

	dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);

	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);

	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);

	dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));



	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);

	dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);

	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,

								pipe_config,

								pipe_bpp / 3);

	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;

	dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));

drivers/gpu/drm/i915/display/intel_dp.h

+4 −0
Original line number Diff line number Diff line
@@ -129,6 +129,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, 
					enum intel_output_format output_format,

					u32 pipe_bpp,

					u32 timeslots);

int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);

int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,

					 struct intel_crtc_state *pipe_config,

					 int bpc);

u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,

				int mode_clock, int mode_hdisplay,

				bool bigjoiner);

drivers/gpu/drm/i915/display/intel_dp_mst.c

+24 −28
Original line number Diff line number Diff line
@@ -164,6 +164,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, 
						      crtc_state->port_clock,

						      crtc_state->lane_count);



	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",

		    min_bpp, max_bpp);



	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {

		struct intel_link_m_n remote_m_n;

		int link_bpp;
@@ -267,8 +270,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, 
	u8 dsc_bpc[3] = {};

	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;

	u8 dsc_max_bpc;

	bool need_timeslot_recalc = false;

	u32 last_compressed_bpp;

	int min_compressed_bpp, max_compressed_bpp;



	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */

	if (DISPLAY_VER(i915) >= 12)
@@ -304,37 +306,31 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, 
	if (max_bpp > sink_max_bpp)

		max_bpp = sink_max_bpp;



	min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));

	max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));



	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,

						     min_bpp, limits,

						     conn_state, 2 * 3, true);

	max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,

								  crtc_state,

								  max_bpp / 3);

	max_compressed_bpp = min(max_compressed_bpp,

				 to_bpp_int(limits->link.max_bpp_x16));



	if (slots < 0)

		return slots;

	min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);

	min_compressed_bpp = max(min_compressed_bpp,

				 to_bpp_int_roundup(limits->link.min_bpp_x16));



	last_compressed_bpp = crtc_state->dsc.compressed_bpp;

	drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",

		    min_compressed_bpp, max_compressed_bpp);



	crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,

									last_compressed_bpp,

	/* Align compressed bpps according to our own constraints */

	max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,

							    crtc_state->pipe_bpp);

	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,

							    crtc_state->pipe_bpp);



	if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)

		need_timeslot_recalc = true;

	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,

						     min_compressed_bpp, limits,

						     conn_state, 1, true);



	/*

	 * Apparently some MST hubs dislike if vcpi slots are not matching precisely

	 * the actual compressed bpp we use.

	 */

	if (need_timeslot_recalc) {

		slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,

							     crtc_state->dsc.compressed_bpp,

							     crtc_state->dsc.compressed_bpp,

							     limits, conn_state, 2 * 3, true);

	if (slots < 0)

		return slots;

	}



	return 0;

}