Commit 99a517a5 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Vinod Koul
Browse files

phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs 



The vendor kernel zeroes out all tuning data outside the init sequence
as part of initialization. Follow suit to avoid UB.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-3-7d8c893d93f6@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 4ba2e527

drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c

+44 −14
Original line number Diff line number Diff line
@@ -24,9 +24,18 @@ 
#define EUSB2_FORCE_VAL_5		0xeD

#define V_CLK_19P2M_EN			BIT(6)



#define EUSB2_TUNE_USB2_CROSSOVER	0x50

#define EUSB2_TUNE_IUSB2		0x51

#define EUSB2_TUNE_RES_FSDIF		0x52

#define EUSB2_TUNE_HSDISC		0x53

#define EUSB2_TUNE_SQUELCH_U		0x54

#define EUSB2_TUNE_USB2_SLEW		0x55

#define EUSB2_TUNE_USB2_EQU		0x56

#define EUSB2_TUNE_USB2_PREEM		0x57

#define EUSB2_TUNE_USB2_HS_COMP_CUR	0x58

#define EUSB2_TUNE_EUSB_SLEW		0x59

#define EUSB2_TUNE_EUSB_EQU		0x5A

#define EUSB2_TUNE_EUSB_HS_COMP_CUR	0x5B



#define QCOM_EUSB2_REPEATER_INIT_CFG(r, v)	\

	{					\
@@ -35,9 +44,18 @@ 
	}



enum reg_fields {

	F_TUNE_EUSB_HS_COMP_CUR,

	F_TUNE_EUSB_EQU,

	F_TUNE_EUSB_SLEW,

	F_TUNE_USB2_HS_COMP_CUR,

	F_TUNE_USB2_PREEM,

	F_TUNE_USB2_EQU,

	F_TUNE_USB2_SLEW,

	F_TUNE_SQUELCH_U,

	F_TUNE_HSDISC,

	F_TUNE_RES_FSDIF,

	F_TUNE_IUSB2,

	F_TUNE_USB2_CROSSOVER,

	F_NUM_TUNE_FIELDS,



	F_FORCE_VAL_5 = F_NUM_TUNE_FIELDS,
@@ -50,9 +68,18 @@ enum reg_fields { 
};



static struct reg_field eusb2_repeater_tune_reg_fields[F_NUM_FIELDS] = {

	[F_TUNE_EUSB_HS_COMP_CUR] = REG_FIELD(EUSB2_TUNE_EUSB_HS_COMP_CUR, 0, 1),

	[F_TUNE_EUSB_EQU] = REG_FIELD(EUSB2_TUNE_EUSB_EQU, 0, 1),

	[F_TUNE_EUSB_SLEW] = REG_FIELD(EUSB2_TUNE_EUSB_SLEW, 0, 1),

	[F_TUNE_USB2_HS_COMP_CUR] = REG_FIELD(EUSB2_TUNE_USB2_HS_COMP_CUR, 0, 1),

	[F_TUNE_USB2_PREEM] = REG_FIELD(EUSB2_TUNE_USB2_PREEM, 0, 2),

	[F_TUNE_USB2_EQU] = REG_FIELD(EUSB2_TUNE_USB2_EQU, 0, 1),

	[F_TUNE_USB2_SLEW] = REG_FIELD(EUSB2_TUNE_USB2_SLEW, 0, 1),

	[F_TUNE_SQUELCH_U] = REG_FIELD(EUSB2_TUNE_SQUELCH_U, 0, 2),

	[F_TUNE_HSDISC] = REG_FIELD(EUSB2_TUNE_HSDISC, 0, 2),

	[F_TUNE_RES_FSDIF] = REG_FIELD(EUSB2_TUNE_RES_FSDIF, 0, 2),

	[F_TUNE_IUSB2] = REG_FIELD(EUSB2_TUNE_IUSB2, 0, 3),

	[F_TUNE_USB2_CROSSOVER] = REG_FIELD(EUSB2_TUNE_USB2_CROSSOVER, 0, 2),



	[F_FORCE_VAL_5] = REG_FIELD(EUSB2_FORCE_VAL_5, 0, 7),

	[F_FORCE_EN_5] = REG_FIELD(EUSB2_FORCE_EN_5, 0, 7),
@@ -62,13 +89,8 @@ static struct reg_field eusb2_repeater_tune_reg_fields[F_NUM_FIELDS] = { 
	[F_RPTR_STATUS] = REG_FIELD(EUSB2_RPTR_STATUS, 0, 7),

};



struct eusb2_repeater_init_tbl {

	unsigned int reg;

	unsigned int val;

};



struct eusb2_repeater_cfg {

	const struct eusb2_repeater_init_tbl *init_tbl;

	const u32 *init_tbl;

	int init_tbl_num;

	const char * const *vreg_list;

	int num_vregs;
@@ -87,10 +109,10 @@ static const char * const pm8550b_vreg_l[] = { 
	"vdd18", "vdd3",

};



static const struct eusb2_repeater_init_tbl pm8550b_init_tbl[] = {

	QCOM_EUSB2_REPEATER_INIT_CFG(F_TUNE_IUSB2, 0x8),

	QCOM_EUSB2_REPEATER_INIT_CFG(F_TUNE_SQUELCH_U, 0x3),

	QCOM_EUSB2_REPEATER_INIT_CFG(F_TUNE_USB2_PREEM, 0x5),

static const u32 pm8550b_init_tbl[F_NUM_TUNE_FIELDS] = {

	[F_TUNE_IUSB2] = 0x8,

	[F_TUNE_SQUELCH_U] = 0x3,

	[F_TUNE_USB2_PREEM] = 0x5,

};



static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
@@ -118,8 +140,9 @@ static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr) 


static int eusb2_repeater_init(struct phy *phy)

{

	struct reg_field *regfields = eusb2_repeater_tune_reg_fields;

	struct eusb2_repeater *rptr = phy_get_drvdata(phy);

	const struct eusb2_repeater_init_tbl *init_tbl = rptr->cfg->init_tbl;

	const u32 *init_tbl = rptr->cfg->init_tbl;

	u32 val;

	int ret;

	int i;
@@ -130,9 +153,16 @@ static int eusb2_repeater_init(struct phy *phy) 


	regmap_field_update_bits(rptr->regs[F_EN_CTL1], EUSB2_RPTR_EN, EUSB2_RPTR_EN);



	for (i = 0; i < rptr->cfg->init_tbl_num; i++)

		regmap_field_update_bits(rptr->regs[init_tbl[i].reg],

					 init_tbl[i].val, init_tbl[i].val);

	for (i = 0; i < F_NUM_TUNE_FIELDS; i++) {

		if (init_tbl[i]) {

			regmap_field_update_bits(rptr->regs[i], init_tbl[i], init_tbl[i]);

		} else {

			/* Write 0 if there's no value set */

			u32 mask = GENMASK(regfields[i].msb, regfields[i].lsb);



			regmap_field_update_bits(rptr->regs[i], mask, 0);

		}

	}



	ret = regmap_field_read_poll_timeout(rptr->regs[F_RPTR_STATUS],

					     val, val & RPTR_OK, 10, 5);