Commit 99a8a4c9 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events intel: Update a spelling in haswell/haswellx 



The spelling of "in-flight" was switched to "inflight".

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20231026003149.3287633-3-irogers@google.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 8a94d3bf

tools/perf/pmu-events/arch/x86/haswell/memory.json

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

        "EventCode": "0xC3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

        "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

        "SampleAfterValue": "100003",

        "UMask": "0x2"

    },

tools/perf/pmu-events/arch/x86/haswellx/memory.json

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

        "EventCode": "0xC3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

        "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

        "SampleAfterValue": "100003",

        "UMask": "0x2"

    },