Commit 99cd4935 authored by Kathiravan Thirumoorthy's avatar Kathiravan Thirumoorthy Committed by Bjorn Andersson
Browse files

clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks 



GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
on the request from dependent clocks. Doing so will result in the
unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
clocks.

Cc: stable@vger.kernel.org
Fixes: d9db07f0 ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: default avatarKathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-2-c8ceb1a37680@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent e641a070

drivers/clk/qcom/gcc-ipq6018.c

+0 −6
Original line number Diff line number Diff line
@@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { 
				&gpll0_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { 
				&gpll0_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -161,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { 
				&gpll6_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -192,7 +189,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { 
				&gpll4_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -243,7 +239,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { 
				&gpll2_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -274,7 +269,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { 
				&nss_crypto_pll_main.clkr.hw },

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

		.flags = CLK_SET_RATE_PARENT,

	},

};