Commit 99fa63d9 authored by Xiao Wang's avatar Xiao Wang Committed by Daniel Borkmann
Browse files

riscv, bpf: Try RVC for reg move within BPF_CMPXCHG JIT 



We could try to emit compressed insn for reg move operation during CMPXCHG
JIT, the instruction compression has no impact on the jump offsets of
following forward and backward jump instructions.

Signed-off-by: default avatarXiao Wang <xiao.w.wang@intel.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
Acked-by: default avatarBjörn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240519050507.2217791-1-xiao.w.wang@intel.com
parent e944fc81

arch/riscv/net/bpf_jit_comp64.c

+4 −2
Original line number Diff line number Diff line
@@ -537,8 +537,10 @@ static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64, 
	/* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */

	case BPF_CMPXCHG:

		r0 = bpf_to_rv_reg(BPF_REG_0, ctx);

		emit(is64 ? rv_addi(RV_REG_T2, r0, 0) :

		     rv_addiw(RV_REG_T2, r0, 0), ctx);

		if (is64)

			emit_mv(RV_REG_T2, r0, ctx);

		else

			emit_addiw(RV_REG_T2, r0, 0, ctx);

		emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) :

		     rv_lr_w(r0, 0, rd, 0, 0), ctx);

		jmp_offset = ninsns_rvoff(8);