Unverified Commit 9a029545 authored by Mark Brown's avatar Mark Brown
Browse files

Add audio support for the MediaTek Genio 350-evk 

Merge series from Alexandre Mergnat <amergnat@baylibre.com>:

This serie aim to add the following audio support for the Genio 350-evk:
- Playback
  - 2ch Headset Jack (Earphone)
  - 1ch Line-out Jack (Speaker)
  - 8ch HDMI Tx
- Capture
  - 1ch DMIC (On-board Digital Microphone)
  - 1ch AMIC (On-board Analogic Microphone)
  - 1ch Headset Jack (External Analogic Microphone)

Of course, HDMI playback need the MT8365 display patches [1] and a DTS
change documented in "mediatek,mt8365-mt6357.yaml".

Applied patch:
- mfd: mt6397-core: register mt6357 sound codec

Test passed:
- mixer-test log: [3]
- pcm-test log: [4]

[1]: https://lore.kernel.org/all/20231023-display-support-v1-0-5c860ed5c33b@baylibre.com/
[2]: https://lore.kernel.org/all/20240313110147.1267793-1-angelogioacchino.delregno@collabora.com/
[3]: https://pastebin.com/pc43AVrT
[4]: https://pastebin.com/cCtGhDpg
[5]: https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/sound/for-next/add-i350-audio-support
parents 97688a9c e1991d10

Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml

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Original line number Diff line number Diff line
@@ -37,6 +37,24 @@ properties: 
  "#interrupt-cells":

    const: 2



  mediatek,hp-pull-down:

    description:

      Earphone driver positive output stage short to

      the audio reference ground.

    type: boolean



  mediatek,micbias0-microvolt:

    description: Selects MIC Bias 0 output voltage.

    enum: [1700000, 1800000, 1900000, 2000000,

           2100000, 2500000, 2600000, 2700000]

    default: 1700000



  mediatek,micbias1-microvolt:

    description: Selects MIC Bias 1 output voltage.

    enum: [1700000, 1800000, 1900000, 2000000,

           2100000, 2500000, 2600000, 2700000]

    default: 1700000



  regulators:

    type: object

    $ref: /schemas/regulator/mediatek,mt6357-regulator.yaml
@@ -83,6 +101,9 @@ examples: 
            interrupt-controller;

            #interrupt-cells = <2>;



            mediatek,micbias0-microvolt = <1700000>;

            mediatek,micbias1-microvolt = <1700000>;



            regulators {

                mt6357_vproc_reg: buck-vproc {

                    regulator-name = "vproc";

Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Audio Front End PCM controller for MT8365



maintainers:

  - Alexandre Mergnat <amergnat@baylibre.com>



properties:

  compatible:

    const: mediatek,mt8365-afe-pcm



  reg:

    maxItems: 1



  "#sound-dai-cells":

    const: 0



  clocks:

    items:

      - description: 26M clock

      - description: mux for audio clock

      - description: audio i2s0 mck

      - description: audio i2s1 mck

      - description: audio i2s2 mck

      - description: audio i2s3 mck

      - description: engen 1 clock

      - description: engen 2 clock

      - description: audio 1 clock

      - description: audio 2 clock

      - description: mux for i2s0

      - description: mux for i2s1

      - description: mux for i2s2

      - description: mux for i2s3



  clock-names:

    items:

      - const: top_clk26m_clk

      - const: top_audio_sel

      - const: audio_i2s0_m

      - const: audio_i2s1_m

      - const: audio_i2s2_m

      - const: audio_i2s3_m

      - const: engen1

      - const: engen2

      - const: aud1

      - const: aud2

      - const: i2s0_m_sel

      - const: i2s1_m_sel

      - const: i2s2_m_sel

      - const: i2s3_m_sel



  interrupts:

    maxItems: 1



  power-domains:

    maxItems: 1



  mediatek,dmic-mode:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Indicates how many data pins are used to transmit two channels of PDM

      signal. 1 means two wires, 0 means one wire. Default value is 0.

    enum:

      - 0 # one wire

      - 1 # two wires



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mediatek,mt8365-clk.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/power/mediatek,mt8365-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        audio-controller@11220000 {

            compatible = "mediatek,mt8365-afe-pcm";

            reg = <0 0x11220000 0 0x1000>;

            #sound-dai-cells = <0>;

            clocks = <&clk26m>,

                     <&topckgen CLK_TOP_AUDIO_SEL>,

                     <&topckgen CLK_TOP_AUD_I2S0_M>,

                     <&topckgen CLK_TOP_AUD_I2S1_M>,

                     <&topckgen CLK_TOP_AUD_I2S2_M>,

                     <&topckgen CLK_TOP_AUD_I2S3_M>,

                     <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,

                     <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,

                     <&topckgen CLK_TOP_AUD_1_SEL>,

                     <&topckgen CLK_TOP_AUD_2_SEL>,

                     <&topckgen CLK_TOP_APLL_I2S0_SEL>,

                     <&topckgen CLK_TOP_APLL_I2S1_SEL>,

                     <&topckgen CLK_TOP_APLL_I2S2_SEL>,

                     <&topckgen CLK_TOP_APLL_I2S3_SEL>;

            clock-names = "top_clk26m_clk",

                          "top_audio_sel",

                          "audio_i2s0_m",

                          "audio_i2s1_m",

                          "audio_i2s2_m",

                          "audio_i2s3_m",

                          "engen1",

                          "engen2",

                          "aud1",

                          "aud2",

                          "i2s0_m_sel",

                          "i2s1_m_sel",

                          "i2s2_m_sel",

                          "i2s3_m_sel";

            interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;

            power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;

            mediatek,dmic-mode = <1>;

        };

    };



...

Documentation/devicetree/bindings/sound/mediatek,mt8365-mt6357.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/sound/mediatek,mt8365-mt6357.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MT8365 ASoC sound card



maintainers:

  - Alexandre Mergnat <amergnat@baylibre.com>



properties:

  compatible:

    const: mediatek,mt8365-mt6357



  pinctrl-names:

    minItems: 1

    items:

      - const: default

      - const: dmic

      - const: miso_off

      - const: miso_on

      - const: mosi_off

      - const: mosi_on



  mediatek,platform:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: The phandle of MT8365 ASoC platform.



patternProperties:

  "^dai-link-[0-9]+$":

    type: object

    description:

      Container for dai-link level properties and CODEC sub-nodes.



    properties:

      codec:

        type: object

        description: Holds subnode which indicates codec dai.



        properties:

          sound-dai:

            maxItems: 1

            description: phandle of the codec DAI



        additionalProperties: false



      link-name:

        description: Indicates dai-link name and PCM stream name

        enum:

          - I2S_IN_BE

          - I2S_OUT_BE

          - PCM1_BE

          - PDM1_BE

          - PDM2_BE

          - PDM3_BE

          - PDM4_BE

          - SPDIF_IN_BE

          - SPDIF_OUT_BE

          - TDM_IN_BE

          - TDM_OUT_BE



      sound-dai:

        maxItems: 1

        description: phandle of the CPU DAI



    required:

      - link-name

      - sound-dai



    additionalProperties: false



required:

  - compatible

  - pinctrl-names

  - mediatek,platform



additionalProperties: false



examples:

  - |

    sound {

        compatible = "mediatek,mt8365-mt6357";

        pinctrl-names = "default",

                        "dmic",

                        "miso_off",

                        "miso_on",

                        "mosi_off",

                        "mosi_on";

        pinctrl-0 = <&aud_default_pins>;

        pinctrl-1 = <&aud_dmic_pins>;

        pinctrl-2 = <&aud_miso_off_pins>;

        pinctrl-3 = <&aud_miso_on_pins>;

        pinctrl-4 = <&aud_mosi_off_pins>;

        pinctrl-5 = <&aud_mosi_on_pins>;

        mediatek,platform = <&afe>;



        /* hdmi interface */

        dai-link-0 {

            link-name = "I2S_OUT_BE";

            sound-dai = <&afe>;



            codec {

                sound-dai = <&it66121hdmitx>;

            };

        };

    };

sound/soc/mediatek/mt8365/mt8365-afe-clk.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * MediaTek 8365 AFE clock control

 *

 * Copyright (c) 2024 MediaTek Inc.

 * Authors: Jia Zeng <jia.zeng@mediatek.com>

 *          Alexandre Mergnat <amergnat@baylibre.com>

 */



#include "mt8365-afe-clk.h"

#include "mt8365-afe-common.h"

#include "mt8365-reg.h"

#include "../common/mtk-base-afe.h"

#include <linux/device.h>

#include <linux/mfd/syscon.h>



static const char *aud_clks[MT8365_CLK_NUM] = {

	[MT8365_CLK_TOP_AUD_SEL] = "top_audio_sel",

	[MT8365_CLK_AUD_I2S0_M] = "audio_i2s0_m",

	[MT8365_CLK_AUD_I2S1_M] = "audio_i2s1_m",

	[MT8365_CLK_AUD_I2S2_M] = "audio_i2s2_m",

	[MT8365_CLK_AUD_I2S3_M] = "audio_i2s3_m",

	[MT8365_CLK_ENGEN1] = "engen1",

	[MT8365_CLK_ENGEN2] = "engen2",

	[MT8365_CLK_AUD1] = "aud1",

	[MT8365_CLK_AUD2] = "aud2",

	[MT8365_CLK_I2S0_M_SEL] = "i2s0_m_sel",

	[MT8365_CLK_I2S1_M_SEL] = "i2s1_m_sel",

	[MT8365_CLK_I2S2_M_SEL] = "i2s2_m_sel",

	[MT8365_CLK_I2S3_M_SEL] = "i2s3_m_sel",

	[MT8365_CLK_CLK26M] = "top_clk26m_clk",

};



int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)

{

	size_t i;

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {

		afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);

		if (IS_ERR(afe_priv->clocks[i])) {

			dev_err(afe->dev, "%s devm_clk_get %s fail\n",

				__func__, aud_clks[i]);

			return PTR_ERR(afe_priv->clocks[i]);

		}

	}

	return 0;

}



void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)

{

	if (clk)

		clk_disable_unprepare(clk);

}



int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,

			    unsigned int rate)

{

	int ret;



	if (clk) {

		ret = clk_set_rate(clk, rate);

		if (ret) {

			dev_err(afe->dev, "Failed to set rate\n");

			return ret;

		}

	}

	return 0;

}



int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,

			      struct clk *parent)

{

	int ret;



	if (clk && parent) {

		ret = clk_set_parent(clk, parent);

		if (ret) {

			dev_err(afe->dev, "Failed to set parent\n");

			return ret;

		}

	}

	return 0;

}



static unsigned int get_top_cg_reg(unsigned int cg_type)

{

	switch (cg_type) {

	case MT8365_TOP_CG_AFE:

	case MT8365_TOP_CG_I2S_IN:

	case MT8365_TOP_CG_22M:

	case MT8365_TOP_CG_24M:

	case MT8365_TOP_CG_INTDIR_CK:

	case MT8365_TOP_CG_APLL2_TUNER:

	case MT8365_TOP_CG_APLL_TUNER:

	case MT8365_TOP_CG_SPDIF:

	case MT8365_TOP_CG_TDM_OUT:

	case MT8365_TOP_CG_TDM_IN:

	case MT8365_TOP_CG_ADC:

	case MT8365_TOP_CG_DAC:

	case MT8365_TOP_CG_DAC_PREDIS:

	case MT8365_TOP_CG_TML:

		return AUDIO_TOP_CON0;

	case MT8365_TOP_CG_I2S1_BCLK:

	case MT8365_TOP_CG_I2S2_BCLK:

	case MT8365_TOP_CG_I2S3_BCLK:

	case MT8365_TOP_CG_I2S4_BCLK:

	case MT8365_TOP_CG_DMIC0_ADC:

	case MT8365_TOP_CG_DMIC1_ADC:

	case MT8365_TOP_CG_DMIC2_ADC:

	case MT8365_TOP_CG_DMIC3_ADC:

	case MT8365_TOP_CG_CONNSYS_I2S_ASRC:

	case MT8365_TOP_CG_GENERAL1_ASRC:

	case MT8365_TOP_CG_GENERAL2_ASRC:

	case MT8365_TOP_CG_TDM_ASRC:

		return AUDIO_TOP_CON1;

	default:

		return 0;

	}

}



static unsigned int get_top_cg_mask(unsigned int cg_type)

{

	switch (cg_type) {

	case MT8365_TOP_CG_AFE:

		return AUD_TCON0_PDN_AFE;

	case MT8365_TOP_CG_I2S_IN:

		return AUD_TCON0_PDN_I2S_IN;

	case MT8365_TOP_CG_22M:

		return AUD_TCON0_PDN_22M;

	case MT8365_TOP_CG_24M:

		return AUD_TCON0_PDN_24M;

	case MT8365_TOP_CG_INTDIR_CK:

		return AUD_TCON0_PDN_INTDIR;

	case MT8365_TOP_CG_APLL2_TUNER:

		return AUD_TCON0_PDN_APLL2_TUNER;

	case MT8365_TOP_CG_APLL_TUNER:

		return AUD_TCON0_PDN_APLL_TUNER;

	case MT8365_TOP_CG_SPDIF:

		return AUD_TCON0_PDN_SPDIF;

	case MT8365_TOP_CG_TDM_OUT:

		return AUD_TCON0_PDN_TDM_OUT;

	case MT8365_TOP_CG_TDM_IN:

		return AUD_TCON0_PDN_TDM_IN;

	case MT8365_TOP_CG_ADC:

		return AUD_TCON0_PDN_ADC;

	case MT8365_TOP_CG_DAC:

		return AUD_TCON0_PDN_DAC;

	case MT8365_TOP_CG_DAC_PREDIS:

		return AUD_TCON0_PDN_DAC_PREDIS;

	case MT8365_TOP_CG_TML:

		return AUD_TCON0_PDN_TML;

	case MT8365_TOP_CG_I2S1_BCLK:

		return AUD_TCON1_PDN_I2S1_BCLK;

	case MT8365_TOP_CG_I2S2_BCLK:

		return AUD_TCON1_PDN_I2S2_BCLK;

	case MT8365_TOP_CG_I2S3_BCLK:

		return AUD_TCON1_PDN_I2S3_BCLK;

	case MT8365_TOP_CG_I2S4_BCLK:

		return AUD_TCON1_PDN_I2S4_BCLK;

	case MT8365_TOP_CG_DMIC0_ADC:

		return AUD_TCON1_PDN_DMIC0_ADC;

	case MT8365_TOP_CG_DMIC1_ADC:

		return AUD_TCON1_PDN_DMIC1_ADC;

	case MT8365_TOP_CG_DMIC2_ADC:

		return AUD_TCON1_PDN_DMIC2_ADC;

	case MT8365_TOP_CG_DMIC3_ADC:

		return AUD_TCON1_PDN_DMIC3_ADC;

	case MT8365_TOP_CG_CONNSYS_I2S_ASRC:

		return AUD_TCON1_PDN_CONNSYS_I2S_ASRC;

	case MT8365_TOP_CG_GENERAL1_ASRC:

		return AUD_TCON1_PDN_GENERAL1_ASRC;

	case MT8365_TOP_CG_GENERAL2_ASRC:

		return AUD_TCON1_PDN_GENERAL2_ASRC;

	case MT8365_TOP_CG_TDM_ASRC:

		return AUD_TCON1_PDN_TDM_ASRC;

	default:

		return 0;

	}

}



static unsigned int get_top_cg_on_val(unsigned int cg_type)

{

	return 0;

}



static unsigned int get_top_cg_off_val(unsigned int cg_type)

{

	return get_top_cg_mask(cg_type);

}



int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;

	unsigned int reg = get_top_cg_reg(cg_type);

	unsigned int mask = get_top_cg_mask(cg_type);

	unsigned int val = get_top_cg_on_val(cg_type);

	unsigned long flags;



	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);



	afe_priv->top_cg_ref_cnt[cg_type]++;

	if (afe_priv->top_cg_ref_cnt[cg_type] == 1)

		regmap_update_bits(afe->regmap, reg, mask, val);



	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);



	return 0;

}



int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;

	unsigned int reg = get_top_cg_reg(cg_type);

	unsigned int mask = get_top_cg_mask(cg_type);

	unsigned int val = get_top_cg_off_val(cg_type);

	unsigned long flags;



	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);



	afe_priv->top_cg_ref_cnt[cg_type]--;

	if (afe_priv->top_cg_ref_cnt[cg_type] == 0)

		regmap_update_bits(afe->regmap, reg, mask, val);

	else if (afe_priv->top_cg_ref_cnt[cg_type] < 0)

		afe_priv->top_cg_ref_cnt[cg_type] = 0;



	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);



	return 0;

}



int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	clk_prepare_enable(afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);

	mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);

	mt8365_afe_enable_afe_on(afe);



	return 0;

}



int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	mt8365_afe_disable_afe_on(afe);

	mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);

	mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);



	return 0;

}



int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)

{

	return 0;

}



int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)

{

	return 0;

}



int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;

	unsigned long flags;



	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);



	afe_priv->afe_on_ref_cnt++;

	if (afe_priv->afe_on_ref_cnt == 1)

		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);



	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);



	return 0;

}



int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;

	unsigned long flags;



	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);



	afe_priv->afe_on_ref_cnt--;

	if (afe_priv->afe_on_ref_cnt == 0)

		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);

	else if (afe_priv->afe_on_ref_cnt < 0)

		afe_priv->afe_on_ref_cnt = 0;



	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);



	return 0;

}



int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)

{

	if (apll1)

		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,

				   AFE_22M_PLL_EN, AFE_22M_PLL_EN);

	else

		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,

				   AFE_24M_PLL_EN, AFE_24M_PLL_EN);



	return 0;

}



int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)

{

	if (apll1)

		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,

				   AFE_22M_PLL_EN, ~AFE_22M_PLL_EN);

	else

		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,

				   AFE_24M_PLL_EN, ~AFE_24M_PLL_EN);



	return 0;

}



int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	mutex_lock(&afe_priv->afe_clk_mutex);



	afe_priv->apll_tuner_ref_cnt[apll]++;

	if (afe_priv->apll_tuner_ref_cnt[apll] != 1) {

		mutex_unlock(&afe_priv->afe_clk_mutex);

		return 0;

	}



	if (apll == MT8365_AFE_APLL1) {

		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,

				   AFE_APLL_TUNER_CFG_MASK, 0x432);

		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,

				   AFE_APLL_TUNER_CFG_EN_MASK, 0x1);

	} else {

		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,

				   AFE_APLL_TUNER_CFG1_MASK, 0x434);

		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,

				   AFE_APLL_TUNER_CFG1_EN_MASK, 0x1);

	}



	mutex_unlock(&afe_priv->afe_clk_mutex);

	return 0;

}



int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	mutex_lock(&afe_priv->afe_clk_mutex);



	afe_priv->apll_tuner_ref_cnt[apll]--;

	if (afe_priv->apll_tuner_ref_cnt[apll] == 0) {

		if (apll == MT8365_AFE_APLL1)

			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,

					   AFE_APLL_TUNER_CFG_EN_MASK, 0x0);

		else

			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,

					   AFE_APLL_TUNER_CFG1_EN_MASK, 0x0);



	} else if (afe_priv->apll_tuner_ref_cnt[apll] < 0) {

		afe_priv->apll_tuner_ref_cnt[apll] = 0;

	}



	mutex_unlock(&afe_priv->afe_clk_mutex);

	return 0;

}



int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	if (apll == MT8365_AFE_APLL1) {

		if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN1])) {

			dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",

				 __func__);

			return 0;

		}

		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);

		mt8365_afe_hd_engen_enable(afe, true);

		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);

		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);

	} else {

		if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN2])) {

			dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",

				 __func__);

			return 0;

		}

		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);

		mt8365_afe_hd_engen_enable(afe, false);

		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);

		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);

	}



	return 0;

}



int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)

{

	struct mt8365_afe_private *afe_priv = afe->platform_priv;



	if (apll == MT8365_AFE_APLL1) {

		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);

		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);

		mt8365_afe_hd_engen_disable(afe, true);

		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);

		clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN1]);

	} else {

		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);

		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);

		mt8365_afe_hd_engen_disable(afe, false);

		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);

		clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN2]);

	}



	return 0;

}

sound/soc/mediatek/mt8365/mt8365-afe-clk.h

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/* SPDX-License-Identifier: GPL-2.0

 *

 * MediaTek 8365 AFE clock control definitions

 *

 * Copyright (c) 2024 MediaTek Inc.

 * Authors: Jia Zeng <jia.zeng@mediatek.com>

 *          Alexandre Mergnat <amergnat@baylibre.com>

 */



#ifndef _MT8365_AFE_UTILS_H_

#define _MT8365_AFE_UTILS_H_



struct mtk_base_afe;

struct clk;



int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe);

void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);

int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate);

int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent);

int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);

int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);

int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe);

int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe);

int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe);

int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe);

int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe);

int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe);

int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);

int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);

int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);

int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);

#endif