Commit 9a497710 authored by Ryan Wanner's avatar Ryan Wanner Committed by Claudiu Beznea
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clk: at91: sama7d65: add sama7d65 pmc driver



Add clock support for SAMA7D65 SoC.

Increase maximum number of valid master clocks. The PMC for the SAMA7D65
requires 9 master clocks.

Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL
requirements.

Signed-off-by: default avatarRyan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/549fa8590fe9b4380e413f8eed87392f28754395.1734723585.git.Ryan.Wanner@microchip.com


[claudiu.beznea: sorted alphanumerically the Makefile entries, reorder
 the code for resource cleanup in sama7d65_pmc_setup()]
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 1c9eb9e6
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@@ -24,4 +24,5 @@ obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
obj-$(CONFIG_SOC_SAMA7D65) += sama7d65.o
obj-$(CONFIG_SOC_SAMA7G5) += sama7g5.o
+1 −1
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@@ -20,7 +20,7 @@

#define PMC_MCR_CSS_SHIFT	(16)

#define MASTER_MAX_ID		4
#define MASTER_MAX_ID		9

#define to_clk_master(hw) container_of(hw, struct clk_master, hw)

+1 −1
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@@ -23,7 +23,7 @@
#define UPLL_DIV		2
#define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)

#define PLL_MAX_ID		7
#define PLL_MAX_ID		9

struct sam9x60_pll_core {
	struct regmap *regmap;
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@@ -151,6 +151,7 @@ static struct syscore_ops pmc_syscore_ops = {
static const struct of_device_id pmc_dt_ids[] = {
	{ .compatible = "atmel,sama5d2-pmc" },
	{ .compatible = "microchip,sama7g5-pmc", },
	{ .compatible = "microchip,sama7d65-pmc", },
	{ /* sentinel */ }
};

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