Commit 9abd613a authored by Thomas Bonnefille's avatar Thomas Bonnefille Committed by Conor Dooley
Browse files

riscv: dts: thead: Fix node ordering in TH1520 device tree 



According to the device tree coding style, nodes shall be ordered by
unit address in ascending order.

Signed-off-by: default avatarThomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 4cece764

arch/riscv/boot/dts/thead/th1520.dtsi

+27 −27
Original line number Diff line number Diff line
@@ -193,6 +193,33 @@ uart0: serial@ffe7014000 { 
			status = "disabled";

		};



		emmc: mmc@ffe7080000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe7080000 0x0 0x10000>;

			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		sdio0: mmc@ffe7090000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe7090000 0x0 0x10000>;

			interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		sdio1: mmc@ffe70a0000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe70a0000 0x0 0x10000>;

			interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		uart1: serial@ffe7f00000 {

			compatible = "snps,dw-apb-uart";

			reg = <0xff 0xe7f00000 0x0 0x100>;
@@ -311,33 +338,6 @@ dmac0: dma-controller@ffefc00000 { 
			status = "disabled";

		};



		emmc: mmc@ffe7080000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe7080000 0x0 0x10000>;

			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		sdio0: mmc@ffe7090000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe7090000 0x0 0x10000>;

			interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		sdio1: mmc@ffe70a0000 {

			compatible = "thead,th1520-dwcmshc";

			reg = <0xff 0xe70a0000 0x0 0x10000>;

			interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sdhci_clk>;

			clock-names = "core";

			status = "disabled";

		};



		timer0: timer@ffefc32000 {

			compatible = "snps,dw-apb-timer";

			reg = <0xff 0xefc32000 0x0 0x14>;