Commit 9accc68b authored by Prashanth K's avatar Prashanth K Committed by Greg Kroah-Hartman
Browse files

usb: dwc3: Add dwc pointer to dwc3_readl/writel 



Use dwc pointer in dwc3_readl() dwc3_writel() instead of passing
the dwc->regs. This would help us access the dwc structure and
log the base address in traces. There's no functional changes in
this patch, just refactoring existing APIs.

Signed-off-by: default avatarPrashanth K <prashanth.k@oss.qualcomm.com>
Acked-by: default avatarThinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://patch.msgid.link/20260114100748.2950103-3-prashanth.k@oss.qualcomm.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent abdd1eef

drivers/usb/dwc3/core.c

+97 −97
Original line number Diff line number Diff line
@@ -114,23 +114,23 @@ void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 
	int i;



	for (i = 0; i < dwc->num_usb3_ports; i++) {

		reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));

		reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(i));

		if (enable && !dwc->dis_u3_susphy_quirk)

			reg |= DWC3_GUSB3PIPECTL_SUSPHY;

		else

			reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;



		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);

		dwc3_writel(dwc, DWC3_GUSB3PIPECTL(i), reg);

	}



	for (i = 0; i < dwc->num_usb2_ports; i++) {

		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));

		reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));

		if (enable && !dwc->dis_u2_susphy_quirk)

			reg |= DWC3_GUSB2PHYCFG_SUSPHY;

		else

			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;



		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);

		dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);

	}

}

EXPORT_SYMBOL_GPL(dwc3_enable_susphy);
@@ -140,7 +140,7 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) 
	unsigned int hw_mode;

	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg = dwc3_readl(dwc, DWC3_GCTL);



	 /*

	  * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and
@@ -155,7 +155,7 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) 


	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));

	reg |= DWC3_GCTL_PRTCAPDIR(mode);

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	dwc3_writel(dwc, DWC3_GCTL, reg);



	dwc->current_dr_role = mode;

	trace_dwc3_set_prtcap(mode);
@@ -216,9 +216,9 @@ static void __dwc3_set_mode(struct work_struct *work) 
	if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||

			DWC3_VER_IS_PRIOR(DWC31, 190A)) &&

			desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {

		reg = dwc3_readl(dwc->regs, DWC3_GCTL);

		reg = dwc3_readl(dwc, DWC3_GCTL);

		reg |= DWC3_GCTL_CORESOFTRESET;

		dwc3_writel(dwc->regs, DWC3_GCTL, reg);

		dwc3_writel(dwc, DWC3_GCTL, reg);



		/*

		 * Wait for internal clocks to synchronized. DWC_usb31 and
@@ -228,9 +228,9 @@ static void __dwc3_set_mode(struct work_struct *work) 
		 */

		msleep(100);



		reg = dwc3_readl(dwc->regs, DWC3_GCTL);

		reg = dwc3_readl(dwc, DWC3_GCTL);

		reg &= ~DWC3_GCTL_CORESOFTRESET;

		dwc3_writel(dwc->regs, DWC3_GCTL, reg);

		dwc3_writel(dwc, DWC3_GCTL, reg);

	}



	spin_lock_irqsave(&dwc->lock, flags);
@@ -254,9 +254,9 @@ static void __dwc3_set_mode(struct work_struct *work) 
				phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);



			if (dwc->dis_split_quirk) {

				reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);

				reg = dwc3_readl(dwc, DWC3_GUCTL3);

				reg |= DWC3_GUCTL3_SPLITDISABLE;

				dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

				dwc3_writel(dwc, DWC3_GUCTL3, reg);

			}

		}

		break;
@@ -306,11 +306,11 @@ u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 
	struct dwc3		*dwc = dep->dwc;

	u32			reg;



	dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,

	dwc3_writel(dwc, DWC3_GDBGFIFOSPACE,

		    DWC3_GDBGFIFOSPACE_NUM(dep->number) |

		    DWC3_GDBGFIFOSPACE_TYPE(type));



	reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);

	reg = dwc3_readl(dwc, DWC3_GDBGFIFOSPACE);



	return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);

}
@@ -332,7 +332,7 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) 
	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)

		return 0;



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg = dwc3_readl(dwc, DWC3_DCTL);

	reg |= DWC3_DCTL_CSFTRST;

	reg &= ~DWC3_DCTL_RUN_STOP;

	dwc3_gadget_dctl_write_safe(dwc, reg);
@@ -347,7 +347,7 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) 
		retries = 10;



	do {

		reg = dwc3_readl(dwc->regs, DWC3_DCTL);

		reg = dwc3_readl(dwc, DWC3_DCTL);

		if (!(reg & DWC3_DCTL_CSFTRST))

			goto done;
@@ -387,12 +387,12 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 
	if (dwc->fladj == 0)

		return;



	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);

	reg = dwc3_readl(dwc, DWC3_GFLADJ);

	dft = reg & DWC3_GFLADJ_30MHZ_MASK;

	if (dft != dwc->fladj) {

		reg &= ~DWC3_GFLADJ_30MHZ_MASK;

		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;

		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);

		dwc3_writel(dwc, DWC3_GFLADJ, reg);

	}

}
@@ -424,10 +424,10 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) 
		return;

	}



	reg = dwc3_readl(dwc->regs, DWC3_GUCTL);

	reg = dwc3_readl(dwc, DWC3_GUCTL);

	reg &= ~DWC3_GUCTL_REFCLKPER_MASK;

	reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);

	dwc3_writel(dwc->regs, DWC3_GUCTL, reg);

	dwc3_writel(dwc, DWC3_GUCTL, reg);



	if (DWC3_VER_IS_PRIOR(DWC3, 250A))

		return;
@@ -455,7 +455,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) 
	 */

	decr = 480000000 / rate;



	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);

	reg = dwc3_readl(dwc, DWC3_GFLADJ);

	reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK

	    &  ~DWC3_GFLADJ_240MHZDECR

	    &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
@@ -466,7 +466,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) 
	if (dwc->gfladj_refclk_lpm_sel)

		reg |=  DWC3_GFLADJ_REFCLK_LPM_SEL;



	dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);

	dwc3_writel(dwc, DWC3_GFLADJ, reg);

}



/**
@@ -569,16 +569,16 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc) 


	evt = dwc->ev_buf;

	evt->lpos = 0;

	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),

	dwc3_writel(dwc, DWC3_GEVNTADRLO(0),

		    lower_32_bits(evt->dma));

	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),

	dwc3_writel(dwc, DWC3_GEVNTADRHI(0),

		    upper_32_bits(evt->dma));

	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),

	dwc3_writel(dwc, DWC3_GEVNTSIZ(0),

		    DWC3_GEVNTSIZ_SIZE(evt->length));



	/* Clear any stale event */

	reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));

	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);

	reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));

	dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);

	return 0;

}
@@ -593,7 +593,7 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 
	 * Exynos platforms may not be able to access event buffer if the

	 * controller failed to halt on dwc3_core_exit().

	 */

	reg = dwc3_readl(dwc->regs, DWC3_DSTS);

	reg = dwc3_readl(dwc, DWC3_DSTS);

	if (!(reg & DWC3_DSTS_DEVCTRLHLT))

		return;
@@ -601,14 +601,14 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 


	evt->lpos = 0;



	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);

	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);

	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK

	dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 0);

	dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 0);

	dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK

			| DWC3_GEVNTSIZ_SIZE(0));



	/* Clear any stale event */

	reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));

	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);

	reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));

	dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);

}



static void dwc3_core_num_eps(struct dwc3 *dwc)
@@ -622,18 +622,18 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) 
{

	struct dwc3_hwparams	*parms = &dwc->hwparams;



	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);

	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);

	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);

	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);

	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);

	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);

	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);

	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);

	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);

	parms->hwparams0 = dwc3_readl(dwc, DWC3_GHWPARAMS0);

	parms->hwparams1 = dwc3_readl(dwc, DWC3_GHWPARAMS1);

	parms->hwparams2 = dwc3_readl(dwc, DWC3_GHWPARAMS2);

	parms->hwparams3 = dwc3_readl(dwc, DWC3_GHWPARAMS3);

	parms->hwparams4 = dwc3_readl(dwc, DWC3_GHWPARAMS4);

	parms->hwparams5 = dwc3_readl(dwc, DWC3_GHWPARAMS5);

	parms->hwparams6 = dwc3_readl(dwc, DWC3_GHWPARAMS6);

	parms->hwparams7 = dwc3_readl(dwc, DWC3_GHWPARAMS7);

	parms->hwparams8 = dwc3_readl(dwc, DWC3_GHWPARAMS8);



	if (DWC3_IP_IS(DWC32))

		parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);

		parms->hwparams9 = dwc3_readl(dwc, DWC3_GHWPARAMS9);

}



static void dwc3_config_soc_bus(struct dwc3 *dwc)
@@ -641,10 +641,10 @@ static void dwc3_config_soc_bus(struct dwc3 *dwc) 
	if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {

		u32 reg;



		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);

		reg = dwc3_readl(dwc, DWC3_GSBUSCFG0);

		reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);

		reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);

		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);

		dwc3_writel(dwc, DWC3_GSBUSCFG0, reg);

	}

}
@@ -668,7 +668,7 @@ static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 
{

	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));

	reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(index));



	/*

	 * Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -706,7 +706,7 @@ static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 
	if (dwc->dis_del_phy_power_chg_quirk)

		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;



	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);

	dwc3_writel(dwc, DWC3_GUSB3PIPECTL(index), reg);



	return 0;

}
@@ -715,7 +715,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 
{

	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));

	reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index));



	/* Select the HS PHY interface */

	switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -727,7 +727,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 
		} else if (dwc->hsphy_interface &&

				!strncmp(dwc->hsphy_interface, "ulpi", 4)) {

			reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;

			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);

			dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);

		} else {

			/* Relying on default value. */

			if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -777,7 +777,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 
	if (dwc->ulpi_ext_vbus_drv)

		reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;



	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);

	dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);



	return 0;

}
@@ -991,15 +991,15 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc) 
{

	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);

	reg = dwc3_readl(dwc, DWC3_GSNPSID);

	dwc->ip = DWC3_GSNPS_ID(reg);



	/* This should read as U3 followed by revision number */

	if (DWC3_IP_IS(DWC3)) {

		dwc->revision = reg;

	} else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {

		dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);

		dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);

		dwc->revision = dwc3_readl(dwc, DWC3_VER_NUMBER);

		dwc->version_type = dwc3_readl(dwc, DWC3_VER_TYPE);

	} else {

		return false;

	}
@@ -1013,7 +1013,7 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) 
	unsigned int hw_mode;

	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg = dwc3_readl(dwc, DWC3_GCTL);

	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;

	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);

	power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
@@ -1091,7 +1091,7 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) 
	if (DWC3_VER_IS_PRIOR(DWC3, 190A))

		reg |= DWC3_GCTL_U2RSTECN;



	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	dwc3_writel(dwc, DWC3_GCTL, reg);

}



static int dwc3_core_get_phy(struct dwc3 *dwc);
@@ -1111,7 +1111,7 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 
	int ret;

	int i;



	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);

	cfg = dwc3_readl(dwc, DWC3_GSBUSCFG0);



	/*

	 * Handle property "snps,incr-burst-type-adjustment".
@@ -1186,7 +1186,7 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 
		break;

	}



	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);

	dwc3_writel(dwc, DWC3_GSBUSCFG0, cfg);

}



static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
@@ -1211,12 +1211,12 @@ static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 
	 * (3x or more) to be within the requirement.

	 */

	scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg = dwc3_readl(dwc, DWC3_GCTL);

	if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||

	    (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {

		reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);

		reg |= DWC3_GCTL_PWRDNSCALE(scale);

		dwc3_writel(dwc->regs, DWC3_GCTL, reg);

		dwc3_writel(dwc, DWC3_GCTL, reg);

	}

}
@@ -1239,7 +1239,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
		tx_maxburst = dwc->tx_max_burst_prd;



		if (rx_thr_num && rx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);

			reg |= DWC31_RXTHRNUMPKTSEL_PRD;



			reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
@@ -1248,11 +1248,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);

			reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);

		}



		if (tx_thr_num && tx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);

			reg |= DWC31_TXTHRNUMPKTSEL_PRD;



			reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
@@ -1261,7 +1261,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);

			reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);

		}

	}
@@ -1272,7 +1272,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 


	if (DWC3_IP_IS(DWC3)) {

		if (rx_thr_num && rx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);

			reg |= DWC3_GRXTHRCFG_PKTCNTSEL;



			reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
@@ -1281,11 +1281,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);

			reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);

		}



		if (tx_thr_num && tx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);

			reg |= DWC3_GTXTHRCFG_PKTCNTSEL;



			reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
@@ -1294,11 +1294,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);

			reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);

		}

	} else {

		if (rx_thr_num && rx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);

			reg |= DWC31_GRXTHRCFG_PKTCNTSEL;



			reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
@@ -1307,11 +1307,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);

			reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);

		}



		if (tx_thr_num && tx_maxburst) {

			reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);

			reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);

			reg |= DWC31_GTXTHRCFG_PKTCNTSEL;



			reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
@@ -1320,7 +1320,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) 
			reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);

			reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);



			dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);

			dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);

		}

	}

}
@@ -1343,7 +1343,7 @@ int dwc3_core_init(struct dwc3 *dwc) 
	 * Write Linux Version Code to our GUID register so it's easy to figure

	 * out which kernel version a bug was found.

	 */

	dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);

	dwc3_writel(dwc, DWC3_GUID, LINUX_VERSION_CODE);



	ret = dwc3_phy_setup(dwc);

	if (ret)
@@ -1408,9 +1408,9 @@ int dwc3_core_init(struct dwc3 *dwc) 
	 * DWC_usb31 controller.

	 */

	if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);

		reg = dwc3_readl(dwc, DWC3_GUCTL2);

		reg |= DWC3_GUCTL2_RST_ACTBITLATER;

		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

		dwc3_writel(dwc, DWC3_GUCTL2, reg);

	}



	/*
@@ -1423,9 +1423,9 @@ int dwc3_core_init(struct dwc3 *dwc) 
	 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.

	 */

	if (DWC3_VER_IS(DWC3, 320A)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);

		reg = dwc3_readl(dwc, DWC3_GUCTL2);

		reg &= ~DWC3_GUCTL2_LC_TIMER;

		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

		dwc3_writel(dwc, DWC3_GUCTL2, reg);

	}



	/*
@@ -1438,13 +1438,13 @@ int dwc3_core_init(struct dwc3 *dwc) 
	 * legacy ULPI PHYs.

	 */

	if (dwc->resume_hs_terminations) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

		reg = dwc3_readl(dwc, DWC3_GUCTL1);

		reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;

		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

		dwc3_writel(dwc, DWC3_GUCTL1, reg);

	}



	if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

		reg = dwc3_readl(dwc, DWC3_GUCTL1);



		/*

		 * Enable hardware control of sending remote wakeup
@@ -1479,7 +1479,7 @@ int dwc3_core_init(struct dwc3 *dwc) 
				reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;

		}



		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

		dwc3_writel(dwc, DWC3_GUCTL1, reg);

	}



	dwc3_config_threshold(dwc);
@@ -1490,9 +1490,9 @@ int dwc3_core_init(struct dwc3 *dwc) 
		int i;



		for (i = 0; i < dwc->num_usb3_ports; i++) {

			reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i));

			reg = dwc3_readl(dwc, DWC3_LLUCTL(i));

			reg |= DWC3_LLUCTL_FORCE_GEN1;

			dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg);

			dwc3_writel(dwc, DWC3_LLUCTL(i), reg);

		}

	}
@@ -1511,9 +1511,9 @@ int dwc3_core_init(struct dwc3 *dwc) 
	 * function is available only from version 1.70a.

	 */

	if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);

		reg = dwc3_readl(dwc, DWC3_GUCTL3);

		reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;

		dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

		dwc3_writel(dwc, DWC3_GUCTL3, reg);

	}



	return 0;
@@ -2437,9 +2437,9 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 
	int ret;



	if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {

		dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &

		dwc->susphy_state = (dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)) &

				    DWC3_GUSB2PHYCFG_SUSPHY) ||

				    (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &

				    (dwc3_readl(dwc, DWC3_GUSB3PIPECTL(0)) &

				    DWC3_GUSB3PIPECTL_SUSPHY);

		/*

		 * TI AM62 platform requires SUSPHY to be
@@ -2469,10 +2469,10 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 
		if (dwc->dis_u2_susphy_quirk ||

		    dwc->dis_enblslpm_quirk) {

			for (i = 0; i < dwc->num_usb2_ports; i++) {

				reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));

				reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));

				reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |

					DWC3_GUSB2PHYCFG_SUSPHY;

				dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);

				dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);

			}



			/* Give some time for USB2 PHY to suspend */
@@ -2532,14 +2532,14 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 
		}

		/* Restore GUSB2PHYCFG bits that were modified in suspend */

		for (i = 0; i < dwc->num_usb2_ports; i++) {

			reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));

			reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));

			if (dwc->dis_u2_susphy_quirk)

				reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;



			if (dwc->dis_enblslpm_quirk)

				reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;



			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);

			dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);

		}



		for (i = 0; i < dwc->num_usb2_ports; i++)
@@ -2721,9 +2721,9 @@ void dwc3_pm_complete(struct dwc3 *dwc) 


	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&

			dwc->dis_split_quirk) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);

		reg = dwc3_readl(dwc, DWC3_GUCTL3);

		reg |= DWC3_GUCTL3_SPLITDISABLE;

		dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

		dwc3_writel(dwc, DWC3_GUCTL3, reg);

	}

}

EXPORT_SYMBOL_GPL(dwc3_pm_complete);

drivers/usb/dwc3/debugfs.c

+16 −16
Original line number Diff line number Diff line
@@ -296,14 +296,14 @@ static void dwc3_host_lsp(struct seq_file *s) 


	reg = DWC3_GDBGLSPMUX_HOSTSELECT(sel);



	dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);

	val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);

	dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);

	val = dwc3_readl(dwc, DWC3_GDBGLSP);

	seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", sel, val);



	if (dbc_enabled && sel < 256) {

		reg |= DWC3_GDBGLSPMUX_ENDBC;

		dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);

		val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);

		dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);

		val = dwc3_readl(dwc, DWC3_GDBGLSP);

		seq_printf(s, "GDBGLSP_DBC[%d] = 0x%08x\n", sel, val);

	}

}
@@ -316,8 +316,8 @@ static void dwc3_gadget_lsp(struct seq_file *s) 


	for (i = 0; i < 16; i++) {

		reg = DWC3_GDBGLSPMUX_DEVSELECT(i);

		dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);

		reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP);

		dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);

		reg = dwc3_readl(dwc, DWC3_GDBGLSP);

		seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", i, reg);

	}

}
@@ -335,7 +335,7 @@ static int dwc3_lsp_show(struct seq_file *s, void *unused) 
		return ret;



	spin_lock_irqsave(&dwc->lock, flags);

	reg = dwc3_readl(dwc->regs, DWC3_GSTS);

	reg = dwc3_readl(dwc, DWC3_GSTS);

	current_mode = DWC3_GSTS_CURMOD(reg);



	switch (current_mode) {
@@ -406,7 +406,7 @@ static int dwc3_mode_show(struct seq_file *s, void *unused) 
		return ret;



	spin_lock_irqsave(&dwc->lock, flags);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg = dwc3_readl(dwc, DWC3_GCTL);

	spin_unlock_irqrestore(&dwc->lock, flags);



	mode = DWC3_GCTL_PRTCAP(reg);
@@ -478,7 +478,7 @@ static int dwc3_testmode_show(struct seq_file *s, void *unused) 
		return ret;



	spin_lock_irqsave(&dwc->lock, flags);

	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg = dwc3_readl(dwc, DWC3_DCTL);

	reg &= DWC3_DCTL_TSTCTRL_MASK;

	reg >>= 1;

	spin_unlock_irqrestore(&dwc->lock, flags);
@@ -577,7 +577,7 @@ static int dwc3_link_state_show(struct seq_file *s, void *unused) 
		return ret;



	spin_lock_irqsave(&dwc->lock, flags);

	reg = dwc3_readl(dwc->regs, DWC3_GSTS);

	reg = dwc3_readl(dwc, DWC3_GSTS);

	if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {

		seq_puts(s, "Not available\n");

		spin_unlock_irqrestore(&dwc->lock, flags);
@@ -585,7 +585,7 @@ static int dwc3_link_state_show(struct seq_file *s, void *unused) 
		return 0;

	}



	reg = dwc3_readl(dwc->regs, DWC3_DSTS);

	reg = dwc3_readl(dwc, DWC3_DSTS);

	state = DWC3_DSTS_USBLNKST(reg);

	speed = reg & DWC3_DSTS_CONNECTSPD;
@@ -639,14 +639,14 @@ static ssize_t dwc3_link_state_write(struct file *file, 
		return ret;



	spin_lock_irqsave(&dwc->lock, flags);

	reg = dwc3_readl(dwc->regs, DWC3_GSTS);

	reg = dwc3_readl(dwc, DWC3_GSTS);

	if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {

		spin_unlock_irqrestore(&dwc->lock, flags);

		pm_runtime_put_sync(dwc->dev);

		return -EINVAL;

	}



	reg = dwc3_readl(dwc->regs, DWC3_DSTS);

	reg = dwc3_readl(dwc, DWC3_DSTS);

	speed = reg & DWC3_DSTS_CONNECTSPD;



	if (speed < DWC3_DSTS_SUPERSPEED &&
@@ -942,10 +942,10 @@ static int dwc3_ep_info_register_show(struct seq_file *s, void *unused) 


	spin_lock_irqsave(&dwc->lock, flags);

	reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number);

	dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);

	dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);



	lower_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0);

	upper_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1);

	lower_32_bits = dwc3_readl(dwc, DWC3_GDBGEPINFO0);

	upper_32_bits = dwc3_readl(dwc, DWC3_GDBGEPINFO1);



	ep_info = ((u64)upper_32_bits << 32) | lower_32_bits;

	seq_printf(s, "0x%016llx\n", ep_info);

drivers/usb/dwc3/drd.c

+38 −38

File changed.

Preview size limit exceeded, changes collapsed.

drivers/usb/dwc3/ep0.c

+10 −10
Original line number Diff line number Diff line
@@ -361,7 +361,7 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc, 


		if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||

		    (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {

			reg = dwc3_readl(dwc->regs, DWC3_DCTL);

			reg = dwc3_readl(dwc, DWC3_DCTL);

			if (reg & DWC3_DCTL_INITU1ENA)

				usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;

			if (reg & DWC3_DCTL_INITU2ENA)
@@ -417,12 +417,12 @@ static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 
	if (set && dwc->dis_u1_entry_quirk)

		return -EINVAL;



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg = dwc3_readl(dwc, DWC3_DCTL);

	if (set)

		reg |= DWC3_DCTL_INITU1ENA;

	else

		reg &= ~DWC3_DCTL_INITU1ENA;

	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	dwc3_writel(dwc, DWC3_DCTL, reg);



	return 0;

}
@@ -441,12 +441,12 @@ static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 
	if (set && dwc->dis_u2_entry_quirk)

		return -EINVAL;



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg = dwc3_readl(dwc, DWC3_DCTL);

	if (set)

		reg |= DWC3_DCTL_INITU2ENA;

	else

		reg &= ~DWC3_DCTL_INITU2ENA;

	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	dwc3_writel(dwc, DWC3_DCTL, reg);



	return 0;

}
@@ -612,10 +612,10 @@ static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 
		return -EINVAL;

	}



	reg = dwc3_readl(dwc->regs, DWC3_DCFG);

	reg = dwc3_readl(dwc, DWC3_DCFG);

	reg &= ~(DWC3_DCFG_DEVADDR_MASK);

	reg |= DWC3_DCFG_DEVADDR(addr);

	dwc3_writel(dwc->regs, DWC3_DCFG, reg);

	dwc3_writel(dwc, DWC3_DCFG, reg);



	if (addr)

		usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
@@ -672,12 +672,12 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 
			 * Enable transition to U1/U2 state when

			 * nothing is pending from application.

			 */

			reg = dwc3_readl(dwc->regs, DWC3_DCTL);

			reg = dwc3_readl(dwc, DWC3_DCTL);

			if (!dwc->dis_u1_entry_quirk)

				reg |= DWC3_DCTL_ACCEPTU1ENA;

			if (!dwc->dis_u2_entry_quirk)

				reg |= DWC3_DCTL_ACCEPTU2ENA;

			dwc3_writel(dwc->regs, DWC3_DCTL, reg);

			dwc3_writel(dwc, DWC3_DCTL, reg);

		}

		break;
@@ -717,7 +717,7 @@ static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 
	dwc->u2sel = le16_to_cpu(timing.u2sel);

	dwc->u2pel = le16_to_cpu(timing.u2pel);



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg = dwc3_readl(dwc, DWC3_DCTL);

	if (reg & DWC3_DCTL_INITU2ENA)

		param = dwc->u2pel;

	if (reg & DWC3_DCTL_INITU1ENA)

drivers/usb/dwc3/gadget.c

+80 −80

File changed.

Preview size limit exceeded, changes collapsed.