Commit 9adf1433 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:

 - Mark som pins as invalid for IRQ use in the Qualcomm driver

 - Fix up the use of device properties on the MA35DX Nuvoton, apparently
   something went sidewise

 - Clear the GPIO debounce settings when going down for suspend in the
   AMD driver. Very good for some AMD laptops that now wake up from
   suspend again!

 - Add the compulsory .can_sleep bool flag in the AW9523 driver, should
   have been there from the beginning, now there are users finding the
   bug

 - Drop some bouncing email address from MAINTAINERS

* tag 'pinctrl-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: aw9523: fix can_sleep flag for GPIO chip
  pinctrl: amd: Clear GPIO debounce for suspend
  pinctrl: nuvoton: Fix boot on ma35dx platforms
  MAINTAINERS: drop bouncing Lakshmi Sowjanya D
  pinctrl: qcom: msm: mark certain pins as invalid for interrupts
parents 73392339 5285b5ed

MAINTAINERS

+1 −2
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@@ -19603,8 +19603,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git 
F:	drivers/pinctrl/intel/









PIN CONTROLLER - KEEMBAY









M:	Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>









S:	Supported









S:	Orphan









F:	drivers/pinctrl/pinctrl-keembay*

















PIN CONTROLLER - MEDIATEK

























drivers/pinctrl/nuvoton/pinctrl-ma35.c



+8
−2






























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@@ -1074,7 +1074,10 @@ static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinct







	u32 idx = 0;









	int ret;



















	for_each_gpiochip_node(dev, child) {









	device_for_each_child_node(dev, child) {









		if (fwnode_property_present(child, "gpio-controller"))









			continue;



















		npctl->nfunctions++;









		npctl->ngroups += of_get_child_count(to_of_node(child));









	}








@@ -1092,7 +1095,10 @@ static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinct







	if (!npctl->groups)









		return -ENOMEM;



















	for_each_gpiochip_node(dev, child) {









	device_for_each_child_node(dev, child) {









		if (fwnode_property_present(child, "gpio-controller"))









			continue;



















		ret = ma35_pinctrl_parse_functions(child, npctl, idx++);









		if (ret) {









			fwnode_handle_put(child);
































drivers/pinctrl/pinctrl-amd.c



+11
−0






























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@@ -979,6 +979,17 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend







				  pin, is_suspend ? "suspend" : "hibernate");









		}



















		/*









		 * debounce enabled over suspend has shown issues with a GPIO









		 * being unable to wake the system, as we're only interested in









		 * the actual wakeup event, clear it.









		 */









		if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) {









			amd_gpio_set_debounce(gpio_dev, pin, 0);









			pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n",









				  pin, is_suspend ? "suspend" : "hibernate");









		}



















		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);









	}










































drivers/pinctrl/pinctrl-aw9523.c



+1
−1






























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@@ -784,7 +784,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)







	gc->set_config = gpiochip_generic_config;









	gc->parent = dev;









	gc->owner = THIS_MODULE;









	gc->can_sleep = false;









	gc->can_sleep = true;



















	return 0;









}
































drivers/pinctrl/qcom/pinctrl-msm.c



+20
−0






























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@@ -1038,6 +1038,25 @@ static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,







	       test_bit(d->hwirq, pctrl->skip_wake_irqs);









}



















static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc,









					 unsigned long *valid_mask,









					 unsigned int ngpios)









{









	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);









	const struct msm_pingroup *g;









	int i;



















	bitmap_fill(valid_mask, ngpios);



















	for (i = 0; i < ngpios; i++) {









		g = &pctrl->soc->groups[i];



















		if (g->intr_detection_width != 1 &&









		    g->intr_detection_width != 2)









			clear_bit(i, valid_mask);









	}









}



















static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)









{









	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);








@@ -1441,6 +1460,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)







	girq->default_type = IRQ_TYPE_NONE;









	girq->handler = handle_bad_irq;









	girq->parents[0] = pctrl->irq;









	girq->init_valid_mask = msm_gpio_irq_init_valid_mask;



















	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);









	if (ret) {